Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Patent metadata

Field	Value
Publication number	US-10032508-B1
Application number	US-201615396224-A
Country	US
Kind code	B1
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

First claim

What is claimed is:

1. An apparatus comprising:
read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and
write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

2. The apparatus of claim 1 , wherein the write setback circuitry is to apply the first setback pulse by coupling a bias voltage to the 3DXP memory cell via a first switch coupled in parallel with the current mirror.

3. The apparatus of claim 2 , wherein the first switch is enabled by a delayed signal derived from an enable signal coupled to a sense amp.

4. The apparatus of claim 1 , wherein the write setback circuitry is to apply the first setback pulse by coupling a bias voltage to the 3DXP memory cell via a first switch coupled between two inputs of a sense amp and a second switch coupling the first switch to the bias voltage.

5. The apparatus of claim 1 , wherein the first magnitude of the first setback pulse is larger than the second magnitude.

6. The apparatus of claim 1 , wherein the first magnitude of the first setback pulse scales with a voltage of a wordline select signal applied to a transistor that couples a wordline to the 3DXP memory cell.

7. The apparatus of claim 1 , wherein during a setback operation the first setback pulse is applied to the 3DXP memory cell for a first period of time and the second setback pulse is applied to the 3DXP memory cell for a second period of time that is shorter than the first period of time.

8. The apparatus of claim 1 , wherein the write setback circuitry is configured to apply the first setback pulse to the 3DXP memory cell upon a determination that the 3DXP memory cell turned on in response to application of the read voltage.

9. The apparatus of claim 1 , wherein the 3DXP memory cell is in a crystalline state prior to the application of the read voltage and wherein the write setback circuitry is to apply the first setback pulse subsequent to the 3DXP memory cell turning on in response to application of the read voltage and prior to the 3DXP memory cell turning off.

10. The apparatus of claim 1 , further comprising sense circuitry to sense, concurrently with application of the first setback pulse, whether the 3DXP memory cell is in an amorphous state or a crystalline state.

11. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a processor to cause circuitry to:
apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and
apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

12. The medium of claim 11 , wherein the first setback pulse is applied by coupling a bias voltage to the 3DXP memory cell via a first switch coupled in parallel with the current mirror.

13. The medium of claim 12 , wherein the first switch is enabled by a delayed signal derived from an enable signal coupled to a sense amp that is to sense whether the 3DXP memory cell is in an amorphous state or a crystalline state.

14. The medium of claim 11 , wherein the first setback pulse is to be applied by coupling a bias voltage to the 3DXP memory cell via a first switch coupled between two inputs of a sense amp and a second switch coupling the first switch to the bias voltage.

15. The medium of claim 11 , wherein the first magnitude of the first setback pulse is larger than the second magnitude.

16. A method comprising:
applying a read voltage to a three dimensional crosspoint (3DXP) memory cell; and
applying a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

17. The method of claim 16 , wherein the first setback pulse is applied by coupling a bias voltage to the 3DXP memory cell via a first switch coupled in parallel with the current mirror.

18. The method of claim 17 , wherein the first switch is enabled by a delayed signal derived from an enable signal coupled to a sense amp that is to sense whether the 3DXP memory cell is in an amorphous state or a crystalline state.

19. The method of claim 16 , wherein the first setback pulse is to be applied by coupling a bias voltage to the 3DXP memory cell via a first switch coupled between two inputs of a sense amp and a second switch coupling the first switch to the bias voltage.

20. The method of claim 16 , wherein the first magnitude of the first setback pulse is larger than the second magnitude.

Assignees

• Intel Corp

Inventors

• Srinivasan Balaji
• Chu Daniel
• Leem Lark-Hoon
• Gorman John
• Taub Mase
• Guliani Sandeep
• Pangal Kiran

Classifications

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title