Metamorphic layers in multijunction solar cells

Patent metadata

Field	Value
Publication number	US-10026860-B2
Application number	US-201313956122-A
Country	US
Kind code	B2
Filing date	Jul 31, 2013
Priority date	Jun 2, 2006
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell comprising providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; and forming a grading interlayer over said second sub cell having a third band gap larger than said second band gap forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mis-matched with respect to said second subcell.

First claim

The invention claimed is:

1. A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell, the method comprising:
providing a first substrate composed of GaAs or Ge for the epitaxial growth of semiconductor material;
growing a first solar subcell on said first substrate having a first band gap;
growing a second solar subcell over said first subcell having a second band gap smaller than said first band gap;
growing a tunnel diode layer over the second solar subcell;
growing an InGaAs buffer layer over the tunnel diode layer, wherein the buffer layer is composed of a crystalline structure, the crystalline structure of the buffer layer consisting of indium, gallium and arsenic; and
growing an InGaAlAs grading interlayer on the InGaAs buffer layer, wherein the InGaAlAs grading interlayer is composed of multiple layers each of which has a crystalline structure, wherein the crystalline structure of each of the multiple layers of the grading interlayer consists of indium, gallium, arsenic and aluminum, and wherein the InGaAlAs grading interlayer has a constant third band gap greater than the second band gap; and
growing a third solar subcell over said grading interlayer having a fourth band gap smaller than said second band gap such that said third solar subcell is lattice mismatched with respect to said second solar subcell,
wherein the InGaAlAs grading interlayer achieves a transition in lattice constant from the second subcell to the third subcell.

2. A method of forming a multijunction solar cell as defined in claim 1 , wherein the buffer layer has a thickness of about 1 micron.

3. A method of forming a multijunction solar cell as defined in claim 1 wherein the constant band gap of the grading interlayer is 1.5 eV, the first solar subcell is composed of InGa(Al)P, the second solar subcell includes an InGaP emitter layer, and the third solar subcell is composed of In 0.30 GaAs.

4. A method of forming a solar cell as defined in claim 1 further comprising:
depositing a bottom contact layer composed of a sequence of Ti/Au/Ag/Au layers over said third solar subcell;
attaching a surrogate second substrate which is perforated with holes over said bottom contact layer; and
subsequently removing the first substrate by a sequence of lapping and/or etching steps.

5. A method of forming a solar cell as defined in claim 1 further comprising:
forming a contact layer over said first substrate; and
subsequent to removing the first substrate, depositing grid lines over the contact layer by evaporation and lithographically patterning.

6. A method of forming a solar cell as defined in claim 5 further comprising attaching a coverglass over the solar cell.

7. A method of forming a solar cell as defined in claim 1 further comprising etching said solar cell so as to form a mesa etched around the periphery of the solar cell.

8. A method of forming a multijunction solar cell as defined in claim 1 , wherein the buffer layer is grown directly on the tunnel diode layer.

9. A method of forming a multijunction solar cell as defined in claim 1 , wherein the tunnel diode layer is part of a p++/n++ tunnel diode.

Assignees

• Solaero Tech Corp

Inventors

• Cornfeld Arthur
• Stan Mark A

Classifications

• Y02E10/544

  Solar cells from Group III-V materials · CPC title

• H01L31/06 Primary

  Electricity · mapped topic

• H01L31/06875

  Electricity · mapped topic

• H01L31/184

  Electricity · mapped topic

• H01L31/1844

  Electricity · mapped topic