Semiconductor device

Patent metadata

Field	Value
Publication number	US-10026809-B1
Application number	US-201715662248-A
Country	US
Kind code	B1
Filing date	Jul 27, 2017
Priority date	Dec 22, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of active patterns protruding from a substrate,
wherein the plurality of active patterns includes a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance;
a gate electrode running across the plurality of active patterns;
a gate spacer on a sidewall of the gate electrode;
a plurality of source/drain regions including a first source/drain region, a second source/drain region and a third source/drain region, each of the plurality of source/drain regions being disposed on a region of one of the plurality of active patterns,
wherein the region of one of the plurality of active patterns is disposed adjacent to a side of the gate electrode;
a first protective insulation pattern disposed on the substrate between the first and second active patterns and below the first and second source/drain regions; and
a second protective insulation pattern disposed on the substrate between the second and third active patterns and below the second and third source/drain regions.

2. The semiconductor device of claim 1 ,
wherein the first protective insulation pattern has a first thickness, and
wherein the second protective insulation pattern has a second thickness less than the first thickness.

3. The semiconductor device of claim 1 , further comprising:
a plurality of contact etch stop patterns each covering a sidewall of one of the plurality of source/drain regions,
wherein the first protective insulation pattern is connected to the gate spacer, and
wherein the second protective insulation pattern is connected to one of the plurality of contact etch stop patterns.

4. The semiconductor device of claim 3 ,
wherein the first protective insulation pattern comprises the same material as a material of the gate spacer, and
wherein the second protective insulation pattern comprises the same material as a material of each of the plurality of contact etch stop patterns.

5. The semiconductor device of claim 1 ,
wherein facing sidewalls of the first source/drain region and the second source/drain region are in contact to each other so that an air gap is disposed in a space defined by the facing sidewalls of the first source/drain region and the second source/drain region, and
wherein the first protective insulation pattern is disposed under the space so that the air gap includes a bottom surface defined by the first protective insulation pattern.

6. The semiconductor device of claim 1 ,
wherein the gate spacer comprises a first gate spacer and a second gate spacer that are sequentially disposed on the sidewall of the gate electrode, and
wherein the first gate spacer and the second gate spacer include different materials from each other.

7. The semiconductor device of claim 6 ,
wherein the first protective insulation pattern comprises a first sub-protective insulation pattern and a second sub-protective insulation pattern that are sequentially stacked on the substrate,
wherein the first sub-protective insulation pattern includes the same material as a material of the first gate spacer, and
wherein the second sub-protective insulation pattern includes the same material as a material of the second gate spacer.

8. The semiconductor device of claim 1 , further comprising:
a first source/drain contact connected in common to the first source/drain region and the second source/drain region; and
a second source/drain contact connected to the third source/drain region.

9. A semiconductor device, comprising:
a substrate having a device isolation pattern;
a pair of a first active pattern and a second active pattern protruding from the device isolation pattern of the substrate and spaced apart at a first distance from each other in a first direction;
a pair of gate electrodes running across the pair of the first active pattern and the second active pattern and spaced apart from each other in a second direction crossing the first direction;
a third active pattern protruding from the device isolation pattern of the substrate and spaced apart at a second distance from the second active pattern adjacent to the third active pattern, the second distance being greater than the first distance;
a pair of gate spacers disposed on facing sidewalls of the pair of gate electrodes, respectively;
a pair of source/drain regions on the pair of the first active pattern and the second active pattern, respectively, between one of the pair of gate electrodes and the other of the pair of gate electrodes;
a first protective insulation pattern on the device isolation pattern between the pair of gate electrodes and between the pair of the first active pattern and the second active pattern; and
a second protective insulation pattern on the device isolation pattern between the second active pattern and the third active pattern.

10. The semiconductor device of claim 9 ,
wherein the first protective insulation pattern has a first thickness, and
wherein the second protective insulation pattern has a second thickness less than the first thickness.

11. The semiconductor device of claim 9 , further comprising:
a contact etch stop pattern covering the pair of source/drain regions,
wherein the first protective insulation pattern is connected to a lower end of each of the pair of gate spacers so that a connected structure of the first protective insulation pattern and the pair of gate spacers is of U-shaped,
wherein the second protective insulation pattern is connected to the contact etch stop pattern, and
wherein the first protective insulation pattern and the second protective insulation pattern are in contact with the device isolation pattern.

12. The semiconductor device of claim 11 ,
wherein one of the pair of source/drain regions and the other of the pair of source/drain regions are in contact to each other so that an air gap has a top surface defined by facing sidewalls of the pair of source/drain regions, and
wherein the air gap has a bottom surface defined by the first protective insulation pattern.

13. The semiconductor device of claim 9 ,
wherein each of the pair of gate spacers comprises a first gate spacer and a second gate spacer that are sequentially disposed on a corresponding one of the facing sidewalls of the pair of gate electrodes,
wherein the first protective insulation pattern comprises a first sub-protective insulation pattern and a second sub-protective insulation pattern that are sequentially stacked on the device isolation pattern, and
wherein the first sub-protective insulation pattern includes the same material as a material of the first gate spacer, and the second sub-protective insulation pattern includes the same material as a material of the second gate spacer.

14. A semiconductor device, comprising:
a device isolation pattern disposed on a substrate, wherein the device isolation pattern includes a first part, a second part and a third part;
a first active pattern protruding from the device isolation pattern;
a second active pattern adjacent to the first active pattern in a first direction and protruding from the device isolation pattern;
a first gate structure disposed on the substrate;
a second gate structure adjacent to the first gate structure in a second direction crossing the first direction,
wherein each of the first active pattern and the second active pattern includes a first region and a second region,
wherein the first gate structure and the second gat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seong Geumjung
• Lee Jeongyun
• Hong Seungsoo
• MIN Kyungseok
• Park Seungju
• Oh Youngmook
• Lim Bora

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L29/0653 Primary

  Electricity · mapped topic