Semiconductor device

Patent metadata

Field	Value
Publication number	US-9412731-B2
Application number	US-201414562788-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Apr 4, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region and a second region different from the first region;
a first active pattern protruding upwardly from the substrate in the first region and a second active pattern protruding upwardly from the substrate in the second region;
first gate structures crossing over the first active pattern and being spaced apart from each other by a first distance and second gate structures crossing over the second active pattern and being spaced apart from each other by a second distance;
a first source/drain region disposed on the first active pattern between the first gate structures; and
a second source/drain region disposed on the second active pattern between the second gate structures,
wherein the first source/drain region includes a lower portion in contact with the first active pattern and an upper portion in contact with the lower portion and spaced apart from the first active pattern, the upper portion including a first upper portion having a width substantially increasing as it extends away from the substrate and a second upper portion having a width substantially decreasing as it extends away from the substrate, and
wherein the second source/drain region includes a first portion in contact with the second active pattern and having a width substantially increasing as it extends away from the substrate, and a second portion in contact with the first portion, spaced apart from the second active pattern, and having a width substantially decreasing as it extends away from the substrate.

2. The semiconductor device of claim 1 , wherein the first distance is greater than the second distance.

3. The semiconductor device of claim 1 , wherein the first active pattern extends in a first direction and the first gate structures extend in a second direction intersecting the first direction,
wherein the first source/drain region has a width in the second direction, and
wherein the lower portion of the first source/drain region has a substantially constant width as it extends away from the substrate in a third direction intersecting both the first direction and the second direction.

4. The semiconductor device of claim 1 , wherein the first active pattern extends in a first direction and the first gate structures extend in a second direction intersecting the first direction,
wherein the first source/drain region has a width in the second direction, and
wherein the lower portion of the first source/drain region has a width substantially decreasing as it extends away from the substrate in a third direction intersecting both the first direction and the second direction.

5. The semiconductor device of claim 1 , wherein the first active pattern extends in a first direction and the first gate structures extend in a second direction intersecting the first direction,
wherein the first source/drain region has a width in the second direction, and
wherein the lower portion of the first source/drain region includes:
a first lower portion having a width substantially increasing as it extends away from the substrate in a third direction perpendicular to both the first direction and the second direction; and
a second lower portion having a width substantially decreasing as it extends away from the substrate in the third direction, and
wherein the first lower portion is provided between the first active pattern and the second lower portion.

6. The semiconductor device of claim 1 , further comprising:
auxiliary spacers provided in the first region and disposed to cover the lower portion of the first source/drain region,
wherein the upper portion of the first source/drain region is exposed by the auxiliary spacers.

7. The semiconductor device of claim 6 , further comprising:
first device isolation patterns disposed at opposite sides of the first active pattern,
wherein the auxiliary spacers are disposed on the first device isolation patterns and are spaced apart from each other with the first active pattern interposed therebetween.

8. The semiconductor device of claim 6 , wherein each of the first gate structures comprises:
a first gate electrode crossing over the first active pattern; and
a first gate spacer on both sidewalls of the first gate electrode,
wherein the first active pattern extends in a first direction and the first gate electrode extends in a second direction intersecting the first direction, and
wherein each of the auxiliary spacers extends in the first direction to be in contact with the first gate spacer.

9. The semiconductor device of claim 8 , wherein the auxiliary spacers include silicon nitride.

10. The semiconductor device of claim 1 , wherein the first source/drain region has a first maximum width at a boundary between the first upper portion and the second upper portion,
wherein the second source/drain region has a second maximum width at a boundary between the first portion and the second portion, and
wherein the first maximum width is smaller than the second maximum width.

11. The semiconductor device of claim 1 , wherein at least one of the first and second source/drain regions comprises:
a first epitaxial layer in contact with the substrate;
a second epitaxial layer on the first epitaxial layer; and
a third epitaxial layer on the second epitaxial layer,
wherein each of the first and second epitaxial layers includes germanium and a germanium concentration of the first epitaxial layer is lower than that of the second epitaxial layer.

12. A semiconductor device comprising:
a substrate including a first region and a second region;
a first active pattern protruding upwardly from the substrate in the first region and a second active pattern upwardly protruding from the substrate in the second region;
first gate structures crossing over the first active pattern and being spaced apart from each other by a first distance and second gate structures crossing over the second active pattern and being spaced apart from each other by a second distance;
a first source/drain region disposed on the first active pattern between the first gate structures;
a second source/drain region disposed on the second active pattern between the second gate structures; and
auxiliary spacers disposed only in the first region, provided to be spaced apart from each other in a direction parallel to a direction in which the first gate structures cross over the first active pattern, and covering a lower portion of the first source/drain region.

13. The semiconductor device of claim 12 , further comprising:
first device isolation patterns disposed at opposite sides of the first active pattern,
wherein the auxiliary spacers are disposed on the first device isolation patterns and are spaced apart from each other with the first active pattern interposed therebetween.

14. The semiconductor device of claim 12 , wherein each of the first gate structures comprises:
a first gate electrode crossing over the first active pattern; and
a first gate spacer on both sidewalls of the first gate electrode,
wherein the auxiliary spacers are connected to the first gate spacer.

15. The semiconductor device of claim 12 , wherein the first source/drain region includes an upper portion exposed by the auxiliary spacers.

16. The semiconductor device of claim 12 , wherein the first source/drain region comprises:
the lower portion being in contact with the first active pattern and having a substantially positively sloped sidewall; and
an upper portion including a first upper portion being connected to the lower portion

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seokhoon
• Koo Bonyoung
• Kim Jinbum
• Kim Chul
• Lee Kwan Heum
• Lee Byeongchan
• Jung Sujin

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title