Imaging device having a third circuit with a region overlapping with a fourth circuit

US9748291B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9748291-B2
Application numberUS-201514859530-A
CountryUS
Kind codeB2
Filing dateSep 21, 2015
Priority dateSep 26, 2014
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An imaging device which offers an image with high quality and is suitable for high-speed operation is provided. The imaging device includes a first region to an n-th region (n is a natural number of 2 or more and 16 or less) each including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first to third circuits each include a transistor in which silicon is used in an active layer or an active region. The fourth circuit includes a photoelectric conversion element and a transistor in which an oxide semiconductor is used in an active layer. The first circuit includes a region overlapping with the fourth circuit. The third circuit includes a region overlapping with the fourth circuit.

First claim

Opening claim text (preview).

The invention claimed is: 1. An imaging device comprising: a first region to an n-th region (n is a natural number of 2 or more and 16 or less); and a first circuit, a second circuit, a third circuit, and a fourth circuit in each of the first region to the n-th region, wherein the first to third circuits each include a transistor including silicon in a channel formation region, wherein the fourth circuit includes a photoelectric conversion element and a transistor including an oxide semiconductor in a channel formation region, wherein the first circuit is configured to read out a first signal from the third circuit, wherein the second circuit is configured to output a second signal for driving the fourth circuit, wherein the third circuit is configured to process a third signal output from the fourth circuit, wherein the fourth circuit is configured to convert light into the third signal, wherein the first circuit includes a region overlapping with the fourth circuit, and wherein the third circuit includes a region overlapping with the fourth circuit. 2. The imaging device according to claim 1 , wherein the oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). 3. The imaging device according to claim 1 , wherein the photoelectric conversion element includes selenium. 4. The imaging device according to claim 1 , wherein the first circuit and the second circuit each include a shift register circuit and a buffer circuit. 5. The imaging device according to claim 1 , wherein the third circuit includes a correlated double sampling circuit, an analog-to-digital converter circuit, and a latch circuit. 6. The imaging device according to claim 1 , wherein the first circuit is divided and positioned in two regions. 7. The imaging device according to claim 1 , wherein the second circuit is divided and positioned in two regions. 8. The imaging device according to claim 1 , wherein the first circuit, the second circuit, and the third circuit are in a first layer, wherein the transistor included in the fourth circuit is in a second layer, wherein the photoelectric conversion element is in a third layer, and wherein the second layer is between the first layer and the third layer. 9. An electronic device comprising: the imaging device according to claim 1 ; and a display device. 10. An imaging device comprising a pixel portion, the imaging device comprising: a first circuit, a second circuit, a third circuit, and a fourth circuit, wherein the first to third circuits each include a transistor including silicon in a channel formation region, wherein the pixel portion includes the fourth circuit, wherein the fourth circuit includes a photoelectric conversion element and a transistor including an oxide semiconductor in a channel formation region, wherein the first circuit is configured to read out a first signal from the third circuit, wherein the second circuit is configured to output a second signal for driving the fourth circuit, wherein the third circuit is configured to process a third signal output from the fourth circuit, wherein the fourth circuit is configured to convert light into the third signal, wherein the first circuit includes a region overlapping with the pixel portion, and wherein the third circuit includes a region overlapping with the pixel portion. 11. The imaging device according to claim 10 , wherein the oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). 12. The imaging device according to claim 10 , wherein the photoelectric conversion element includes selenium. 13. The imaging device according to claim 10 , wherein the first circuit and the second circuit each include a shift register circuit and a buffer circuit. 14. The imaging device according to claim 10 , wherein the third circuit includes a correlated double sampling circuit, an analog-to-digital converter circuit, and a latch circuit. 15. The imaging device according to claim 10 , wherein the first circuit is divided and positioned in two regions. 16. The imaging device according to claim 10 , wherein the second circuit is divided and positioned in two regions. 17. The imaging device according to claim 10 , wherein the first circuit, the second circuit, and the third circuit are in a first layer, wherein the transistor included in the fourth circuit is in a second layer, wherein the photoelectric conversion element is in a third layer, and wherein the second layer is between the first layer and the third layer. 18. An electronic device comprising: the imaging device according to claim 10 ; and a display device.

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What does patent US9748291B2 cover?
An imaging device which offers an image with high quality and is suitable for high-speed operation is provided. The imaging device includes a first region to an n-th region (n is a natural number of 2 or more and 16 or less) each including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first to third circuits each include a transistor in which silicon is used in a…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L27/14612. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).