Semiconductor device

Patent metadata

Field	Value
Publication number	US-10014403-B2
Application number	US-201715437559-A
Country	US
Kind code	B2
Filing date	Feb 21, 2017
Priority date	Dec 16, 2013
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first nitride semiconductor layer formed over a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a trench that penetrates the fourth nitride semiconductor layer and ends above a bottom surface of the third nitride semiconductor layer;
a gate electrode disposed by way of a gate insulation film in the trench;
a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode; and
a coupling portion for coupling the first electrode and the first nitride semiconductor layer,
wherein an electron affinity of the third nitride semiconductor layer is larger than an electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than the electron affinity of the second nitride semiconductor layer,
wherein the first nitride semiconductor layer contains a p-type or an n-type impurity,
wherein the coupling portion is disposed inside a through hole that penetrates the fourth nitride semiconductor layer, the third nitride semiconductor layer, and the second nitride semiconductor layer and reaches as far as the first nitride semiconductor layer, and
wherein a bottom of the through hole is situated at a surface of the first nitride semiconductor layer or in the middle of the first nitride semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first electrode is disposed over the coupling portion.

3. The semiconductor device according to claim 1 , wherein the first nitride semiconductor layer contains a p-type impurity.

4. The semiconductor device according to claim 1 , wherein a super lattice layer is interposed between the substrate and the first nitride semiconductor layer, and
wherein the super lattice layer comprises two or more stacks each comprising a fifth nitride semiconductor layer and a sixth nitride semiconductor layer having an electron affinity different from that of the filth nitride semiconductor layer and disposed repetitively.

5. The semiconductor device according to claim 1 , wherein a terminal potion, which is electrically coupled with the first electrode, is disposed over the coupling portion.

6. The semiconductor device according to claim 1 , wherein a bottom surface of the trench is located above the bottom surface of the third nitride semiconductor layer.

7. A semiconductor device, comprising:
a first nitride semiconductor layer formed over a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a gate electrode disposed by way of a fifth nitride semiconductor layer over the fourth nitride semiconductor layer;
a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode; and
a coupling portion for coupling the first electrode and the first nitride semiconductor layer,
wherein an electron affinity of the third nitride semiconductor layer is larger than an electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than the electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fifth nitride semiconductor layer is larger than the electron affinity of the fourth nitride semiconductor layer,
wherein the first nitride semiconductor layer contains a p-type or an n-type impurity,
wherein the substrate includes a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region includes a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer, and
wherein the coupling portion is disposed inside a through hole that penetrates the device isolation region and the second nitride semiconductor layer, and reaches as far as the first nitride semiconductor layer.

8. The semiconductor device according to claim 7 , wherein a terminal portion elect idly coupled with the first electrode is disposed over the coupling portion.

9. The semiconductor device according to claim 7 , wherein a bottom of the through hole is situated at a surface of the first nitride semiconductor layer or in a middle of the first nitride semiconductor layer.

10. A semiconductor device, comprising:
a first nitride semiconductor layer formed over a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a gate electrode disposed by way of a fifth nitride semiconductor layer over the fourth nitride semiconductor layer;
a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode; and
a coupling portion for coupling the first electrode and the first nitride semiconductor layer,
wherein an electron affinity of the third nitride semiconductor layer is larger than an electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than the electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fifth nitride semiconductor layer is larger than the electron affinity of the fourth nitride semiconductor layer,
wherein the first nitride semiconductor layer contains a p-type or an n-type impurity,
wherein the coupling portion is disposed inside a through hole that penetrates the fourth nitride semiconductor layer, the third nitride semiconductor layer, and the second nitride semiconductor layer, and reaches as far as the first nitride semiconductor layer,
wherein the substrate includes a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region includes a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer, and
wherein the coupling portion is disposed inside the through hole, the through hole penetrating the device isolation region.

11. The semiconductor device according to claim 10 , wherein a bottom surface of the through hole is located above a bottom surface of the first nitride semiconductor layer.

Assignees

• Renesas Electronics Corp

Inventors

• Nakayama Tatsuo
• Miyamoto Hironobu
• Okamoto Yasuhiro
• Miura Yoshinao
• Inoue Takashi

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/0274

  Electricity · mapped topic

• H01L29/1075

  Electricity · mapped topic