Semiconductor device

Patent metadata

Field	Value
Publication number	US-9601609-B2
Application number	US-201414569492-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 16, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Characteristics of a semiconductor device are improved.
A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first nitride semiconductor layer formed over a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a trench that penetrates the fourth nitride semiconductor layer and ends above a bottom surface of the third nitride semiconductor layer;
a gate electrode disposed by way of a gate insulation film in the trench;
a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode; and
a coupling portion for coupling the first electrode and the first nitride semiconductor layer,
wherein an electron affinity of the third nitride semiconductor layer is larger than an electron affinity of the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than the electron affinity of the second nitride semiconductor layer,
wherein the first nitride semiconductor layer contains a p-type or n-type impurity,
wherein the substrate includes a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein a device isolation region is formed in the second region adjacent to the first region, and
wherein the coupling portion is disposed inside a through hole that penetrates the device isolation region and reaches as far as the first nitride semiconductor layer.

2. The semiconductor device according to claim 1 , wherein a first terminal portion electrically coupled with the first electrode is disposed over the coupling portion.

3. The semiconductor device according to claim 1 , wherein a bottom of the through hole is situated below the first nitride semiconductor layer.

4. The semiconductor device according to claim 1 , wherein a bottom of the through hole is situated at a surface of the first nitride semiconductor layer or in the middle of the first nitride semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the first nitride semiconductor layer contains a p-type impurity.

6. The semiconductor device according to claim 1 , wherein a super lattice layer is interposed between the substrate and the first nitride semiconductor layer, and
wherein the super lattice layer includes two or more stacks each comprising a fifth nitride semiconductor layer and a sixth nitride semiconductor layer having an electron affinity different from that of the fifth nitride semiconductor layer and disposed repetitively.

Assignees

• Renesas Electronics Electronics
• Renesas Electronics Corp

Inventors

• Nakayama Tatsuo
• Miyamoto Hironobu
• Okamoto Yasuhiro
• Miura Yoshinao
• Inoue Takashi

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/1087

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic