Semiconductor device

Patent metadata

Field	Value
Publication number	US-9520489-B2
Application number	US-201514604796-A
Country	US
Kind code	B2
Filing date	Jan 26, 2015
Priority date	Feb 5, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first nitride semiconductor layer that is made over a substrate;
a second nitride semiconductor layer that is formed on the first nitride semiconductor layer;
a third nitride semiconductor layer that is formed on the second nitride semiconductor layer;
a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer;
a trench that penetrates through the fourth nitride semiconductor layer, and reaches a middle portion of the third nitride semiconductor layer;
a gate electrode that is arranged within the trench through a gate insulating film;
a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on both sides of the gate electrode;
a first connection portion that connects the first electrode to the first nitride semiconductor layer;
a second connection portion that connects the second electrode to the second nitride semiconductor layer; and
an insulating film that is formed between the first connection portion and the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer,
wherein the first nitride semiconductor layer contains impurities of a first conductivity type,
wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type,
wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region is an device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer,
wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer, and
wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion.

2. The semiconductor device according to claim 1 ,
wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer.

3. The semiconductor device according to claim 1 ,
wherein a first terminal portion that is electrically coupled to the first electrode is arranged on the first connection portion.

4. The semiconductor device according to claim 3 ,
wherein a second terminal portion that is electrically coupled to the second electrode is arranged on the second connection portion.

5. The semiconductor device according to claim 1 ,
wherein a fifth nitride semiconductor layer is arranged under the first nitride semiconductor layer, and
wherein the fifth nitride semiconductor layer contains the first conductivity type impurities higher in concentration than the first nitride semiconductor layer.

6. The semiconductor device according to claim 5 ,
wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region, the second nitride semiconductor layer, and the first nitride semiconductor layer, and reaches the fifth nitride semiconductor layer.

7. The semiconductor device according to claim 5 ,
wherein a superlattice layer is arranged between the substrate and first nitride semiconductor layer, and
wherein in the superlattice layer, two or more stacked bodies having a sixth nitride semiconductor layer, and a seventh nitride semiconductor layer different in electron affinity from the sixth nitride semiconductor layer are repetitively arranged.

8. The semiconductor device according to claim 1 ,
wherein the second connection portion is arranged within a second through-hole that penetrates through the fourth nitride semiconductor layer and the third nitride semiconductor layer, and reaches the second nitride semiconductor layer.

9. The semiconductor device according to claim 8 ,
wherein the second electrode is arranged on the second connection portion.

10. The semiconductor device according to claim 1 ,
wherein the first connection portion comprises a first conductive film, and the second connection portion comprises a second conductive film.

11. The semiconductor device according to claim 1 ,
wherein the first connection portion comprises a first metal film, and the second connection portion comprises a second metal film.

12. A semiconductor device, comprising:
a first nitride semiconductor layer that is made over a substrate;
a second nitride semiconductor layer that is formed on the first nitride semiconductor layer;
a third nitride semiconductor layer that is formed on the second nitride semiconductor layer;
a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer;
a gate electrode that is arranged above the fourth nitride semiconductor layer through the fifth nitride semiconductor layer;
a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on both sides of the gate electrode;
a first connection portion that connects the first electrode to the first nitride semiconductor layer;
a second connection portion that connects the second electrode to the second nitride semiconductor layer; and
an insulating film that is formed between the first connection portion and the second nitride semiconductor layer,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer,
wherein an electron affinity of the fifth nitride semiconductor layer is larger than an electron affinity of the fourth nitride semiconductor layer,
wherein the first nitride semiconductor layer contains impurities of a first conductivity type,
wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type,
wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region is a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer,
wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer,
wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion, and
wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer.

13. The semiconductor device according to claim 12 ,
wherein the second connection portion is arranged within the second through-hole that penetrates through the fourth nitride semiconductor layer and the third nitride semiconductor layer, and reaches the second nitride semiconductor layer.

14. The semiconductor device according to claim 13 ,
wherein the second electrode is arranged on the second connection portion.

Assignees

• Renesas Electronics Corp

Inventors

• Nakayama Tatsuo
• Miyamoto Hironobu
• Okamoto Yasuhiro
• Miura Yoshinao
• Inoue Takashi

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/021

  of FETs having insulated gates [IGFET] · CPC title

• H10D64/693 Primary

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title