Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications
US-8946829-B2 · Feb 3, 2015 · US
Non-planar transistor
US9117909B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9117909-B2 |
| Application number | US-201414470957-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 28, 2014 |
| Priority date | Apr 16, 2013 |
| Publication date | Aug 25, 2015 |
| Grant date | Aug 25, 2015 |
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Abstract
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A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
First claim
Opening claim text (preview).
What is claimed is: 1. A non-planar transistor, comprising: a substrate having an active region and an isolation region, wherein the isolation region encompasses the active region; a plurality of shallow trenches disposed in the substrate in the active region, wherein a portion of the substrate between each two shallow trenches is defined as a protruding structure, and the protruding structure has an upper portion having a substantially vertical sidewall and a lower portion havi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9117909B2 cover?
- A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin st…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6211. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 25 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).