Shallow trench isolation for end fin variation control

Patent metadata

Field	Value
Publication number	US-9252044-B2
Application number	US-201414223106-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 24, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.

First claim

What is claimed is:

1. A method of fabricating a fin field effect transistor (FinFET) device including both shallow and deep shallow trench isolation (STI) regions, the method comprising:
forming a deep STI region adjacent to a first side of an end fin among a plurality of fins;
lining the deep STI region, including the first side of the end fin, with a passivation layer;
depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin;
etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap extending from a sidewall of the STI oxide to the first side of the end fin, the gap being located directly between the sidewall of the STI oxide and the first side of the end fin; and
depositing gate material, the gate material covering the gap.

2. The method according to claim 1 , wherein the lining the deep STI region with the passivation layer includes lining the deep STI region with silicon nitride (SiN).

3. The method according to claim 1 , wherein the depositing the gate material includes depositing a polysilicon.

4. The method according to claim 1 , wherein the etching to the specified depth includes etching the passivation layer such that a same depth of the end fin is exposed on the first side as on a second side, the second side being an opposite side of the end fin.

5. The method according to claim 4 , wherein the etching the passivation layer such that the same depth of the end fin is exposed on the first side and on the second side includes forming a same channel width on both sides of the end fin.

6. The method according to claim 1 , wherein the lining the deep STI region with the passivation layer includes re-depositing the passivation layer after removing the passivation layer to form the deep STI region.

7. The method according to claim 6 , wherein the removing the passivation layer to form the deep STI region includes removing the passivation layer adjacent to the first side of the end fin.

8. The method according to claim 1 , further comprising forming the plurality of fins based on spacers comprising silicon dioxide (SiO 2 ).

9. The method according to claim 8 , further comprising forming the spacers based on using amorphous silicon as mandrels.

10. The method according to claim 9 , wherein the spacers define a pitch of the plurality of fins.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title