Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions

Patent metadata

Field	Value
Publication number	US-2017005014-A1
Application number	US-201514789476-A
Country	US
Kind code	A1
Filing date	Jul 1, 2015
Priority date	Jul 1, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

First claim

1 . A test structure of a fin-type field effect transistor (FinFET) comprising:
a first conducting layer electrically coupled to a dummy gate of the FinFET; a second conducting layer electrically coupled to a substrate of the FinFET; a third conducting layer electrically coupled to the dummy gate of the FinFET; a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer; and a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer; wherein the first region comprises a first dielectric having a first dimension; and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

2 . The test structure of claim 1 , wherein the first conducting layer is electrically coupled to the dummy gate by a first local interconnect and a first via.

3 . The test structure of claim 2 , wherein the second conducting layer is electrically coupled to the substrate by a second local interconnect and a second via.

4 . The test structure of claim 3 , wherein the third conducting layer is electrically coupled to the dummy gate by a third local interconnect and a third via.

5 . The test structure of claim 1 , wherein a first capacitance between the first conducting layer and the second conducting layer corresponds to the first dielectric region.

6 . The test structure of claim 5 , wherein the first capacitance between the first conducting layer and the second conducting layer corresponds to the first dimension.

7 . The test structure of claim 6 , wherein a second capacitance between the second conducting layer and the third conducting layer corresponds to a second dielectric.

8 . The test structure of claim 7 , wherein the second capacitance between the second conducting layer and the third conducting layer corresponds to the second dimension.

9 . The test structure of claim 1 further comprising:
a fourth conducting layer electrically coupled to the dummy gate of the FinFET; and
a third region of the FinFET at least partially bound by the second conducting layer and the fourth conducting layer;
wherein the third region comprises a third dielectric having a third dimension greater than the first dimension.

10 . The test structure of claim 1 , wherein:
a third capacitance between the second conducting layer and the fourth conducting layer corresponds to a third dielectric; and the third capacitance between the second conducting layer and the fourth conducting layer corresponds to the third dimension.

11 . A method of forming a test structure of a fin-type field effect transistor (FinFET), the method comprising:
forming a first conducting layer; electrically coupling the first conducting layer to a dummy gate of the FinFET; forming a second conducting layer; electrically coupling the second conducing layer to a substrate of the FinFET; forming a third conducting layer; and electrically coupling the third conducting layer to the dummy gate of the FinFET; wherein the formation of the first conducing layer and the second conducting layer define boundaries of a first region of the FinFET; and wherein the formation of the second conducting layer and the third conducting layer define boundaries of a second region of the FinFET.

12 . The method of claim 11 , wherein:
the first region comprises a dielectric having a first dimension.

13 . The method of claim 12 , wherein:
the second region comprises a dielectric having a second dimension greater than the first dimension.

14 . The method of claim 11 , wherein the electrical coupling of the first conducing layer to the dummy gate comprises a first local interconnect and a first via.

15 . The method of claim 11 , wherein the electrical coupling of the second conducting layer to the substrate comprises a second local interconnect and a second via.

16 . The method of claim 11 , wherein the electrical coupling of the third conducting layer to the dummy gate comprise a third local interconnect and a third via.

17 . The method of claim 11 further comprising:
measuring a first capacitance between the first conducting layer and the second conducting layer;
wherein the first capacitance corresponds to the first region; and
wherein the first capacitance corresponds to the first dimension.

18 . The method of claim 17 further comprising:
measuring a second capacitance between the second conducting layer and the third conducting layer;
wherein the second capacitance corresponds to the second dimension.

19 . The method of claim 12 further comprising:
forming a fourth conducting layer; and
electrically coupling the fourth conducting layer to the dummy gate of the FinFET;
wherein a third region of the FinFET is at least partially bound by the second conducting layer and the fourth conducting layer; and
wherein the third region comprises a third dielectric having a third dimension greater than the first dimension.

20 . The method of claim 19 further comprising:
measuring a third capacitance between the second conducting layer and the fourth conducting layer;
wherein the third capacitance corresponds to the third dielectric; and
wherein the third capacitance corresponds to the third dimension.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Yamashita Tenko
• Yeh Chun-Chen
• Zang Hui

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10W20/0698

  Local interconnections · CPC title