Capacitors in integrated circuits and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-10008560-B2
Application number	US-201615241931-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Oct 27, 2010
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
depositing a first insulating layer over a workpiece;
forming first metal bars and first vias in the first insulating layer over a first region of the workpiece, wherein a bottom surface of the first metal bars facing the workpiece is coplanar with a bottom surface of the first vias facing the workpiece, the first metal bars oriented along a first direction;
forming a second insulating layer over the first insulating layer;
forming metal lines over a second region of the workpiece and not directly over the first metal bars;
forming a third insulating layer over the second insulating layer; and
forming second metal bars in the third insulating layer over the first region of the workpiece, wherein the second metal bars are oriented along the first direction, and wherein the second metal bars do not conductively contact any of the underlying first metal bars between a bottom surface of the second metal bars and a top surface of the first metal bars that directly underlies the bottom surface of the second metal bars.

2. The method of claim 1 , wherein the first metal bars are parallel to the second metal bars, wherein each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, and wherein each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

3. The method of claim 2 , wherein each of the second metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the middle portions of the second metal bars and the second ends of the second metal bars do not contact any metal line, wherein each of the first ends of the first metal bars contact a second metal line in a second metal level, and wherein each of the first ends of the second metal bars contact the second metal line.

4. The method of claim 1 , wherein forming first metal bars comprises:
forming openings for first metal bars in the first insulating layer; and
filling the openings for first metal bars with a conductive fill material.

5. The method of claim 1 , further comprising:
forming a third metal bar in the first insulating layer, the third metal bar oriented perpendicular to the first metal bars, wherein each of the first metal bars contact the third metal bar; and
forming a fourth metal bar in the third insulating layer, the fourth metal bar oriented perpendicular to the second metal bars, wherein each of the second metal bars contact the fourth metal bar.

6. The method of claim 5 , further comprising forming a metal line in the second insulating layer, the metal line contacting the third metal bar and the fourth metal bar.

7. The method of claim 1 , wherein the first metal bars have a longer length than the first vias.

8. A method of fabricating a semiconductor device, the method comprising:
forming first metal bars and first vias in a first via level, the first metal bars having a longer length than the first vias, wherein a bottom surface of the first metal bars is coplanar with a bottom surface of the first vias, wherein a top surface of the first metal bars facing away from a substrate is coplanar with a top surface of the first vias facing away from the substrate, wherein the first metal bars are oriented along a first direction; and
forming second metal bars and second vias in a second via level, the second via level being above the first via level, the second metal bars having a longer length than the second vias, wherein the second metal bars are coupled to the first metal bars, wherein the second metal bars are formed laterally adjacent to the second vias in the second via level, wherein the first metal bars are parallel to the second metal bars, wherein each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line, wherein each of the second metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, wherein the second metal bars are oriented along the first direction, wherein each of the middle portions of the second metal bars and the second ends of the second metal bars do not conductively contact any of the underlying first metal bars between the bottom surface of the second metal bars and the top surface of the first metal bars that directly underlies the bottom surface of the second metal bars, and does not conductively contact any other metal line, and wherein each of the first ends of the first metal bars contact a third metal bar disposed in the first via level, the third metal bar oriented perpendicular to the first metal bars.

9. The method of claim 8 , wherein the first ends of the first metal bars contact a first metal line in a first metal level.

10. The method of claim 8 , wherein each of the first ends of the first metal bars contact a second metal line in a second metal level, and wherein each of the first ends of the second metal bars contact the second metal line.

11. The method of claim 10 , wherein each of the first ends of the first metal bars is coupled to each of the first ends of the second metal bars through the second metal line.

12. The method of claim 8 , wherein each of the first ends of the second metal bars contact a fourth metal bar disposed in the second via level, the fourth metal bar oriented perpendicular to the second metal bars.

13. The method of claim 12 , further comprising forming a metal line in a second metal level contacting the third metal bar and the fourth metal bar.

14. The method of claim 8 , further comprising:
forming fourth metal bars, parallel to the first metal bars, in the first via level, the fourth metal bars being capacitively coupled to the first metal bars, wherein each of the fourth metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends, and wherein each of the middle portions of the fourth metal bars and the second ends of the fourth metal bars do not contact any metal line; and
forming fifth metal bars, parallel to the second metal bars, in the second via level, the fifth metal bars being coupled to the fourth metal bars.

15. The method of claim 8 , wherein the first metal bars are laterally offset from the second metal bars.

16. The method of claim 8 , wherein the first metal bars extend into a first metal level, and wherein the first metal bars have the same shape within the first via level and the first metal level.

17. The method of claim 8 , wherein the first metal bars are staggered relative to the second metal bars.

18. A method of fabricating a semiconductor device, the method comprising:
forming first metal bars and first vias in a first via level over a semiconductor substrate, the first metal bars having a longer length than the first vias, wherein a bottom surface of the first metal bars facing the semiconductor substrate is coplanar with a bottom surface of the first vias facing the semiconductor substrate; and
forming second metal bars and second vias in a second via level, the second metal bars coupled to the first metal bars, the second via level being above the first via level, the second metal bars having a longer length than the second vias, wherein the first metal bars are parallel to the second metal ba

Assignees

• Infineon Technologies Ag

Inventors

• Kim Sun-Oo
• Chae Moosung
• Moon Bum Ki

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L23/5223

  Electricity · mapped topic

• H01L28/90

  Electricity · mapped topic

• H01L28/87 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic