Testing a non-core MMU

Patent metadata

Field	Value
Publication number	US-10007568-B2
Application number	US-201615096989-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Jan 6, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

First claim

What is claimed is:

1. A method for testing a non-core memory management unit (MMU) using an MMU testor, the method comprising:
transmitting one or more translation requests from the MMU testor to the non-core MMU disposed on a processor chip, in order to test the non-core MMU, wherein the non-core MMU is external to a processing core of the processor chip, wherein no processing core in the processor chip can transmit translation requests to the non-core MMU, and wherein the MMU testor is disposed on a computing component external to the processor chip;
receiving one or more memory translation results from the non-core MMU at the MMU testor, wherein the one or more translation requests include a virtual memory address;
comparing, using the MMU testor, the one or more memory translation results received from the non-core MMU to one or more expected results, wherein the one or more expected results include a physical memory address that corresponds to the virtual memory address; and
detecting an error in the non-core MMU, using the MMU testor, based on determining that at least one of the memory translation results does not match the respective expected result.

2. The method of claim 1 , wherein the computing component is a field-programmable gate array (FPGA), the method further comprising:
executing the MMU testor using circuit elements in the FPGA.

3. The method of claim 2 , wherein transmitting translation requests from a MMU testor to a non-core MMU comprises:
transmitting data between the FPGA and the processor chip using a PCIe link.

4. The method of claim 1 , further comprising:
transmitting an interrupt from the MMU testor to the processing core upon determining that one or more of the memory translation results received from the non-core MMU do not match the respective one or more expected results.

5. The method of claim 1 , wherein non-core hardware is disposed in the processor chip, wherein the non-core hardware is communicatively coupled to the non-core MMU in the processor chip for performing memory translations.

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti
• Lecocq Paul F
• Schumann John A

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G06F11/2231

  to test interrupt circuits · CPC title