Testing a non-core mmu

Patent metadata

Field	Value
Publication number	US-2017192869-A1
Application number	US-201614989187-A
Country	US
Kind code	A1
Filing date	Jan 6, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

First claim

1 . A computing system, comprising:
a non-core memory management unit (MMU) disposed in a processor chip, wherein the non-core MMU is external to a processing core of the processor chip; a communication link coupling the processor chip to a computing component external to the processor chip; and a MMU testor disposed on the computing component, wherein the MMU testor is configured to transmit translation requests to the non-core MMU and receive memory translation results from the non-core MMU.

2 . The computing system of claim 1 , wherein no processing core in the processor chip can transmit translation requests to the non-core MMU.

3 . The computing system of claim 1 , wherein the computing component is a field-programmable gate array (FPGA), wherein the MMU testor is executed by circuit elements in the FPGA.

4 . The computing system of claim 3 , wherein the communication link implements a PCIe protocol to transmit data between the FPGA and the processor chip.

5 . The computing system of claim 1 , wherein the MMU testor is configured to compare the memory translation results received from the non-core MMU to expected results to identify a flaw in a design of the non-core MMU.

6 . The computing system of claim 5 , wherein the MMU testor is configured to transmit an interrupt to the processing core upon detecting a flaw in the design of the non-core MMU.

7 . The computing system of claim 1 , further comprising: non-core hardware disposed in the processor chip, wherein the non-core hardware is communicatively coupled to the non-core MMU in the processor chip, and wherein the non-core hardware is configured to, during execution of the processor chip, transmit memory translation requests to the non-core MMU.

8 .- 14 . (canceled)

15 . A system, comprising:
a computer processor; and a memory containing a program that, when executed on the computer processor, performs an operation in a simulated computing environment, the operation comprising:
simulating a non-core MMU in a simulated processor chip, wherein the non-core MMU is external to a processing core of the simulated processor chip;
simulating a MMU testor in a simulated computing component external to the processor chip;
simulating a communication link between the simulated processor chip and the simulated computing component;
transmitting translation requests from the MMU testor to the non-core MMU, and;
receiving memory translation results from the non-core MMU at the MMU testor.

16 . The system of claim 15 , wherein no processing core in the simulated processor chip can transmit translation requests to the non-core MMU in the simulated computing environment.

17 . The system of claim 15 , wherein the computing component is a simulated FPGA, the operation further comprising:
executing the MMU testor using circuit elements in the simulated FPGA.

18 . The system of claim 15 , wherein the operation further comprises:
comparing the memory translation results received from the non-core MMU to expected results to identify a flaw in a design of the non-core MMU.

19 . The system of claim 15 , wherein the operation further comprises:
simulating non-core hardware disposed in the processor chip, wherein the non-core hardware is communicatively coupled to the non-core MMU in the simulated processor chip for performing memory translations.

20 . The system of claim 15 , wherein non-core hardware is disposed in the simulated processor chip, wherein the non-core hardware is communicatively coupled to the non-core MMU in the simulated processor chip for performing memory translations.

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti
• Lecocq Paul F
• Schumann John A

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/2736

  using a dedicated service processor for test · CPC title

• G06F11/261 Primary

  by simulating additional hardware, e.g. fault simulation · CPC title