Device-Level Interconnects for Stacked Transistor Structures and Methods of Fabrication Thereof
US-2025351506-A1 · Nov 13, 2025 · US
Yang Liang-Yueh Ou is listed as an inventor on 7 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Yang Liang-Yueh Ou |
| Total patents | 7 |
| First publication | Dec 8, 2015 |
| Latest publication | Nov 13, 2025 |
Publications ranked by popularity score, then publication date.
US-2025351506-A1 · Nov 13, 2025 · US
US-2024413211-A1 · Dec 12, 2024 · US
US-12068197-B2 · Aug 20, 2024 · US
US-2021257254-A1 · Aug 19, 2021 · US
US-9632498-B2 · Apr 25, 2017 · US
US-9476135-B2 · Oct 25, 2016 · US
US-9209073-B2 · Dec 8, 2015 · US
Latest publications not already listed above.
No data yet.
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 8 |
| Taiwan Semiconductor Mfg | 1 |
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/033 | 5 |
| H10P14/47 | 4 |
| H10W20/056 | 4 |
| H01L21/76877 | 4 |
| H01L21/2885 | 4 |