Systems and methods of compensating for filling material losses in electroplating processes

Patent metadata

Field	Value
Publication number	US-9632498-B2
Application number	US-201313870025-A
Country	US
Kind code	B2
Filing date	Apr 25, 2013
Priority date	Mar 12, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
determining, using a computer, a local pattern density magnitude gradient along circuit patterns, each comprising a respective plurality of objects, in adjacent cells of a plurality of cells of an integrated circuit layout wherein the adjacent cells are disposed along an electroplating process flow direction;
determining, using the computer, a respective pattern perimeter sum parameter as a sum of the respective perimeter magnitudes of each of the respective objects in each of the respective circuit patterns in the adjacent cells;
selecting a dummy pattern having a pattern density magnitude between respective pattern density magnitudes of the circuit patterns in the adjacent cells so as to compensate for an estimated loss of filling material during electrochemical plating induced by the local pattern density magnitude gradient exceeding a threshold pattern density magnitude gradient for circuit patterns in the adjacent cells, wherein the selected dummy pattern has a respective pattern perimeter sum parameter between the respectively determined pattern perimeter sum parameters for the circuit patterns in the adjacent cells;
inserting the selected dummy pattern at a boundary between the circuit patterns in the adjacent cells of the layout; and
controlling an electroplating process based on the layout.

2. The method of claim 1 , wherein the filling material is copper (Cu).

3. The method of claim 1 , wherein the integrated circuit layout is for a conductive line layer.

4. The method of claim 1 , wherein the integrated circuit layout is for an interconnect layer.

5. The method of claim 1 , wherein the threshold pattern density magnitude gradient for circuit patterns in adjacent cells is a magnitude between about 5 and about 20.

6. The method of claim 1 , wherein the threshold pattern density magnitude gradient for circuit patterns in adjacent cells is a magnitude of approximately 10.

7. The method of claim 1 , further comprising:
generating a revised integrated circuit layout having the selected dummy pattern inserted at the boundary between the circuit patterns in the adjacent cells.

8. The method of claim 7 , further comprising:
causing a display device to graphically display the revised integrated circuit layout.

9. The method of claim 1 , further comprising:
depositing the filling material using the electrochemical plating process.

10. A non-transitory computer readable storage medium encoded with computer program instructions, such that when a processor executes the computer program instructions, the processor performs a method comprising:
determining a local pattern density magnitude gradient along circuit patterns disposed in cells adjacent to each other and along an electroplating process flow direction wherein the adjacent cells are respective cells of an integrated circuit layout and wherein the respective circuit patterns in the adjacent cells each comprise a respective plurality of objects;
comparing the determined local pattern density magnitude gradient with a threshold pattern density magnitude gradient for circuit patterns in adjacent cells;
determining a respective sum of respective perimeter magnitudes of each of the plurality of objects in each of the respective circuit patterns in the adjacent cells;
selecting a dummy pattern based on the comparison and having a respective pattern perimeter sum parameter between the respectively determined sums for the circuit patterns in the adjacent cells so as to compensate for an estimated loss of filling material at a transition point between the circuit patterns in the adjacent cells and during an electrochemical plating process along the process flow direction;
inserting the selected dummy pattern at the transition point between the circuit patterns in the adjacent cells of the layout; and
controlling an electroplating process based on the layout.

11. The computer readable storage medium of claim 10 , encoded with computer program instructions, such that when the processor executes the computer program instructions, the processor performs the method further comprising:
causing a display device to display a revised integrated circuit layout including the selected dummy pattern inserted at the transition point between the circuit patterns in the adjacent cells.

12. The computer readable storage medium of claim 10 , wherein the integrated circuit layout is for a layer selected from the group consisting of: a conductive line layer and a via layer; and wherein the adjacent cells are disposed along an edge of the layout.

13. The method of claim 10 , further comprising:
depositing filling material based on the layout.

14. A computer-implemented method, comprising:
receiving an initial layout in a computer, the initial layout comprising a plurality of cells in a grid, wherein respective integrated circuit patterns, each comprising a respective plurality of objects, are disposed in respective cells of the plurality of cells and wherein a group of cells in a region of the grid are adjacent to another group of cells in another region of the grid, and wherein the adjacent cells are disposed along an electroplating process flow direction;
analyzing the initial layout to determine a respective sum of respective perimeter magnitudes of each of the respective objects in each circuit pattern in the adjacent cells and a pattern density magnitude gradient along circuit patterns in the adjacent cells;
comparing the determined pattern density magnitude gradient with a threshold pattern density magnitude gradient for circuit patterns in adjacent cells stored in a tangible, non-transitory machine readable storage medium;
generating a revised layout in the computer based on the comparison including dummy patterns selected based on the determined pattern density magnitude gradient and positioned at a boundary between the circuit patterns in the adjacent cells so as to compensate for an estimated loss of filling material during an electrochemical plating process in the adjacent cells, wherein one or more of the selected dummy patterns has a respective pattern perimeter sum parameter between the respectively determined sums for the circuit patterns in the adjacent cells; and
controlling an electroplating process based on the revised layout.

15. The method of claim 14 , further comprising:
displaying the revised layout.

16. The method of claim 14 , further comprising:
determining at the computer the respective pattern density magnitudes of the circuit patterns in the adjacent cells; and
wherein the selected dummy patterns have respective pattern density magnitudes between the respectively determined pattern density magnitudes of the circuit patterns in the adjacent cells.

17. The method of claim 14 , further comprising:
depositing filling material based on the revised layout.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chih-Yi
• Yang Liang-Yueh Ou
• Kao Chen-Yuan
• Su Hung-Wen

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• G05B19/41835 Primary

  characterised by program execution · CPC title

• H01L21/76877

  Electricity · mapped topic