Data compression engine
US-12574448-B2 · Mar 10, 2026 · US
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Wang Weihuang patents
Wang Weihuang is listed as an inventor on 126 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wang Weihuang |
| Total patents | 126 |
| First publication | Apr 7, 2015 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Resource Isolation In A Hardware-Assisted Transport Layer
US-2025358239-A1 · Nov 20, 2025 · US
Efficient hash table lookup
US-12475167-B2 · Nov 18, 2025 · US
High bandwidth content addressable memory (CAM) based hardware architecture for datacenter networking
US-12443657-B2 · Oct 14, 2025 · US
Policer synchronization across multiple pipelines in a dpu
US-2025298630-A1 · Sep 25, 2025 · US
Programmable traffic ingress direction for reduced latency in a DPU
US-12423255-B1 · Sep 23, 2025 · US
Policer synchronization across multiple pipelines in a DPU
US-12423116-B1 · Sep 23, 2025 · US
Programmable traffic ingress direction for reduced latency in a dpu
US-2025291753-A1 · Sep 18, 2025 · US
High performance connection scheduler
US-12363204-B1 · Jul 15, 2025 · US
Method and apparatus for flexible and efficient analytics in a network switch
US-2025158910-A1 · May 15, 2025 · US
Recent patents
Latest publications not already listed above.
Hierarchical statisically multiplexed counters and a method thereof
US-12231124-B2 · Feb 18, 2025 · US
Method and apparatus for flexible and efficient analytics in a network switch
US-12224941-B2 · Feb 11, 2025 · US
Packet cache system and method
US-12216587-B2 · Feb 4, 2025 · US
Early retransmission for hardware reliable transport
US-12184417-B2 · Dec 31, 2024 · US
Off-chip memory backed reliable transport connection cache hardware architecture
US-12132802-B2 · Oct 29, 2024 · US
Reliable transport protocol and hardware architecture for datacenter networking
US-12132800-B2 · Oct 29, 2024 · US
Acknowledgement coalescing module utilized in content addressable memory (CAM) based hardware architecture for data center networking
US-12040988-B2 · Jul 16, 2024 · US
High performance cache eviction
US-12019542-B2 · Jun 25, 2024 · US
Packet Cache System and Method
US-2024193093-A1 · Jun 13, 2024 · US
Packet cache system and method
US-11995000-B2 · May 28, 2024 · US
Efficient Hash Table Lookup
US-2024168996-A1 · May 23, 2024 · US
Rate update engine for reliable transport protocol
US-11979330-B2 · May 7, 2024 · US
High performance connection scheduler
US-11979476-B2 · May 7, 2024 · US
Flow table aging optimized for DRAM access
US-11960413-B2 · Apr 16, 2024 · US
High Performance Connection Scheduler
US-2024121320-A1 · Apr 11, 2024 · US
High Performance Memory Allocator
US-2024111667-A1 · Apr 4, 2024 · US
Hybrid wildcard match table
US-11943142-B2 · Mar 26, 2024 · US
Efficient hash table lookup
US-11914647-B2 · Feb 27, 2024 · US
Data Compression Engine
US-2024064215-A1 · Feb 22, 2024 · US
Hierarchical statisically multiplexed counters and a method thereof
US-2024063800-A1 · Feb 22, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 42 |
| Cavium Inc | 36 |
| Marvell Asia Pte Ltd | 22 |
| Xpliant Inc | 18 |
| Cavium Llc | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L45/74591 | 22 |
| H04L45/54 | 19 |
| H04L49/9084 | 13 |
| H04L45/7457 | 13 |
| H03K23/64 | 12 |