Acknowledgement coalescing module utilized in content addressable memory (CAM) based hardware architecture for data center networking

Patent metadata

Field	Value
Publication number	US-12040988-B2
Application number	US-202117552767-A
Country	US
Kind code	B2
Filing date	Dec 16, 2021
Priority date	May 25, 2021
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including an acknowledgment coalescing module in communication with a content addressable memory (CAM). The acknowledgment coalescing module coalesces multiple acknowledgement packets as a single acknowledgement packet to reduce the overall numbers of the packet transmission in the communication protocol system. In addition, the acknowledgment coalescing module may also provide a piggyback mechanism to carry acknowledge information in a regular data packet. Thus, the need to generate a new acknowledgement packet may be eliminated. Accordingly, the network congestion and latency may be reduced, and the communication and transmission efficiency are enhanced.

First claim

The invention claimed is:

1. A computing system, comprising:
a content addressable memory;
a data storage device;
an acknowledgment coalescing module configured in the data storage device configured to be in communication with the content addressable memory; and
one or more processors in communication with the content addressable memory and the acknowledgment coalescing module, the one or more processors configured to:
receive one or more data packets;
generate one or more acknowledgement packets in response to receiving the one or more data packets;
perform a lookup operation to access data entries stored in the content addressable memory; and
when a match is found between the accessed data entries and the generated one or more acknowledgement packets, coalesce the one or more acknowledgement packets in the acknowledgment coalescing module.

2. The computing system of claim 1 , wherein the one or more processors are further configured to:
when a match is not found between the accessed data entries and the generated one or more acknowledgement packets, install a new data entry in the content addressable memory.

3. The computing system of claim 1 , wherein the one or more processors are further configured to:
evict the coalesced acknowledgement packets as a single acknowledgment packet when a pre-programmed threshold of acknowledgement packet count is reached.

4. The computing system of claim 1 , wherein the one or more processors are further configured to:
piggyback an acknowledgment message in the one or more acknowledgment packets.

5. The computing system of claim 3 , wherein the one or more processors are further configured to:
uninstall the data entries in the content addressable memory after the coalesced acknowledgement packets are evicted.

6. The computing system of claim 1 , wherein the one or more processors are further configured to:
evict the one or more acknowledgement packets immediately when occupancy of the data storage device reaches a pre-programmed threshold.

7. The computing system of claim 1 , wherein the one or more processors are further configured to:
perform a background scan in the acknowledgment coalescing module; and
evict the one or more acknowledgement packets when a pre-programmed threshold of acknowledgement coalescing time is reached.

8. The computing system of claim 1 , wherein the lookup operation further causes the one or more processors to:
look up a connection ID in the data entries in the content addressable memory related to the one or more acknowledgement packets.

9. The computing system of claim 1 , wherein the one or more acknowledgement packets comprises information of a base sequence number and a sequence number bitmap.

10. A method, comprising:
receiving, by one or more processors, one or more data packets in a computing system;
generating, by the one or more processors, one or more acknowledgement packets in response to the one or more data packets;
performing, by the one or more processors, a lookup operation to access data entries stored in a content addressable memory in the computing system; and
when a match is found between the accessed data entries and the generated one or more acknowledgement packets, coalescing the one or more acknowledgement packets in an acknowledgment coalescing module.

11. The method of claim 10 , further comprising:
installing, by one or more processors, a new data entry in the content addressable memory when a match is not found between the accessed data entries and the generated one or more acknowledgement packets.

12. The method of claim 10 , further comprising:
evicting, by one or more processors, the coalesced acknowledgement packets as a single acknowledgment packet when a pre-programmed threshold of acknowledgement packet count is reached.

13. The method of claim 12 , wherein evicting the coalesced acknowledgement packets as the single acknowledgment packet further comprises:
piggybacking, by the one or more processors, an acknowledgment message in the one or more acknowledgment packets.

14. The method of claim 10 , further comprising:
evicting, by the one or more processors, the one or more acknowledgement packets immediately when the one or more data packets includes an acknowledgment requested mark set therein.

15. The method of claim 12 , further comprising:
uninstalling, by the one or more processors, the data entries in the content addressable memory after the coalesced acknowledgement packets are evicted.

16. The method of claim 10 , further comprising:
performing a background scan, by the one or more processors, in the acknowledgment coalescing module; and
evicting, by the one or more processors, the one or more acknowledgement packets when a pre-programmed threshold of acknowledgement coalescing time is reached.

17. The method of claim 10 , wherein the lookup operation comprises:
looking up, by the one or more processors, a connection ID or packet sequence number in the data entries in the content addressable memory related to the one or more acknowledgement packets.

18. The method of claim 10 , wherein the one or more acknowledgement packets comprises information of a base sequence number and a sequence number bitmap.

19. The method of claim 11 , wherein the computing system is configured to perform a remote direct memory access operation.

20. A method, comprising:
coalescing, by one or more processors, multiple acknowledgement packets to generate a single coalesced acknowledgement packet in an acknowledgment coalescing module implemented in a computing system, the acknowledgment coalescing module communicating with a content addressable memory storing data entries;
evicting the single coalesced acknowledgement packet to an initiator entity in the computing system; and
uninstalling the data entries in the content addressable memory after the coalesced acknowledgment packet is evicted.

Assignees

• Google Llc

Inventors

• Vaduvatha Srinivas
• Wang Weihuang
• Zheng Jiazhen
• Chandra Prashant

Classifications

• H04L67/1097

  for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

• H04L1/187

  Details of sliding window management · CPC title

• H04L1/1832

  Details of sliding window management · CPC title

• H04L1/1614

  using bitmaps · CPC title

• H04L47/34 Primary

  ensuring sequence integrity, e.g. using sequence numbers · CPC title