Off-chip memory backed reliable transport connection cache hardware architecture

Patent metadata

Field	Value
Publication number	US-12132802-B2
Application number	US-202117553387-A
Country	US
Kind code	B2
Filing date	Dec 16, 2021
Priority date	Sep 1, 2021
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.

First claim

The invention claimed is:

1. An application specific integrated circuit (ASIC) of a network interface card, including:
a reliable transport accelerator (RTA) including a cache lookup database, wherein the RTA is configured to:
determine, from a received data packet, a connection identifier;
query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier; and
receive, in response to the query, a cache hit or a cache miss, wherein:
the network interface card includes off-chip memory storing one or more connection contexts associated with one or more connection identifiers,
the off-chip memory is positioned on the network interface card and connected to the ASIC, and
the RTA communicates with the off-chip memory via a network-on-chip (NOC).

2. The ASIC of claim 1 , wherein the ASIC further includes on-chip memory storing one or more connection contexts associated with one or more connection identifiers.

3. The ASIC of claim 2 , wherein a cache miss indicates that the connection context having the connection identifier is not stored in the cache lookup database.

4. The ASIC of claim 3 , wherein, after receiving a cache miss, the RTA retrieves the connection context from the on-chip memory or the off-chip memory.

5. The ASIC of claim 4 , wherein the RTA stores the connection context in the on-chip memory or the off-chip memory based on a predefined user configuration.

6. The ASIC of claim 1 , wherein a cache hit indicates that the connection context having the connection identifier is stored in the cache lookup database.

7. The ASIC of claim 6 , further including a cache policy stored by the cache lookup database, wherein the cache policy defines when one or more connection contexts are evicted from the cache lookup database.

8. The ASIC of claim 7 , wherein evicted connection contexts are moved to on-chip or off-chip memory.

9. The ASIC of claim 1 further comprising an upper-layer protocol accelerator (ULP) and a packet process pipeline accelerator.

10. The ASIC of claim 1 , wherein the RTA further includes a context flush interface, and the RTA is further configured to:
dynamically fetch and update connection context at run-time; and
update, using the context flush interface, the context connections stored in the cache lookup database.

11. The ASIC of claim 1 , wherein:
the RTA further includes a reliable transport protocol partitioned into at least two layers, and
the at least two layers of protocols include a solicitation layer configured to end-point admission control and a sliding window layer configured for end-to-end reliable delivery and congestion control.

12. The ASIC of claim 1 , wherein the RTA communicates with the off-chip memory for managing connection contexts with the off-chip memory.

13. A method for managing connection contexts, the method including:
determining, by a reliable transport accelerator (RTA) including a cache lookup database, a connection identifier for a received data packet;
querying, by the RTA, the cache lookup database for a cache entry corresponding to a connection context having the connection identifier; and
receiving, from the cache lookup database, in response to the query, a cache hit or a cache miss,
wherein:
the RTA communicates with off-chip memory via a network-on-chip (NOC),
the off-chip memory stores one or more connection contexts associated with one or more connection identifiers,
the off-chip memory is positioned on a network interface card and connected to an application specific integrated circuit (ASIC) of the network interface card.

14. The method of claim 13 , wherein a cache miss indicates that the connection context having the connection identifier is not stored in the cache lookup database.

15. The method of claim 14 , wherein, after receiving a cache miss, the RTA retrieves the connection context from on-chip memory or off-chip memory.

16. The method of claim 15 , wherein the RTA stores the connection context in the on-chip memory or the off-chip memory based on a predefined user configuration.

17. The method of claim 13 , wherein a cache hit indicates that the connection context having the connection identifier is stored in the cache lookup database.

18. The method of claim 13 , wherein the RTA further includes a cache policy stored by the cache lookup database, wherein the cache policy defines when one or more connection contexts are evicted from the cache lookup database.

19. The method of claim 18 , wherein evicted connection contexts are moved to on-chip or off-chip memory.

20. The method of claim 19 , wherein the on-chip memory is located on an ASIC with the RTA.

Assignees

• Google Llc

Inventors

• Wang Weihuang
• Vaduvatha Srinivas
• Wang Xiaoming
• Rajamani Gurushankar
• Agarwal Abhishek
• Zheng Jiazhen
• Chandra Prashant

Classifications

• H04L69/326

  in the transport layer [OSI layer 4] (H04L69/16 takes precedence) · CPC title

• H04L49/3063

  Pipelined operation · CPC title

• G06F16/24552

  Database cache management · CPC title

• H04L49/254

  Centralised controller, i.e. arbitration or scheduling · CPC title

• H04L67/568 Primary

  Storing data temporarily at an intermediate stage, e.g. caching · CPC title