Hierarchical statisically multiplexed counters and a method thereof

Patent metadata

Field	Value
Publication number	US-12231124-B2
Application number	US-202318500091-A
Country	US
Kind code	B2
Filing date	Nov 1, 2023
Priority date	Jun 11, 2014
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

First claim

We claim:

1. A counter architecture implemented in a network device, the counter architecture comprising:
a mirrored shift logic; and
a hierarchy of levels of statistically multiplexed counters, wherein each level of the hierarchy of levels includes N counters arranged in rows having P base counters, and further wherein the mirrored shift logic extends the P base counters to a full width such that a full range of shifting is reduced.

2. The network device of claim 1 , wherein counters in the same row in one level of the hierarchy of levels are shuffled into different rows in a next level above of the hierarchy of levels.

3. The network device of claim 2 , wherein a randomization of the shuffle is a bit reverse of a counter identifier of a counter, a hash function or a bit arrangement in another order.

4. The network device of claim 1 , wherein the counter architecture is configured to update a counter by:
determining whether a corresponding row of the counter in a current level of the hierarchy of levels overflows;
based on the determination that the corresponding row in the current level does not overflow, processing each level below the current level by using a first routine and processing the current level by using a second routine; and
based on the determination that the corresponding row in the current level does overflow, determining whether a corresponding row of the counter in a next level above overflows;
based on the determination that the corresponding row of the counter in the next level above does not overflow, processing each level below the next level above by using the first routine and processing the next level above by using the second routine; and
based on the determination that the corresponding row of the counter in the next level above does overflow, when the next level above is not the highest level in the hierarchy of levels, returning to the step of determining whether a corresponding row of the counter in a next level above overflows, and when the next level above is the highest level in the hierarchy of levels, processing the next level above and each level below the next level above by using the first routine and updating an overflow queue.

5. The network device of claim 4 , wherein the first routine includes incrementing the counter in the corresponding level and shrinking the counter in the corresponding level.

6. The network device of claim 4 , wherein the second routine includes incrementing the counter in the corresponding level.

7. The network device of claim 6 , wherein the incrementing the counter includes expanding a size of the counter in the corresponding level.

8. The network device of claim 4 , wherein updating the overflow queue includes pushing a counter identifier of the counter and an overflow width into the overflow queue.

9. The network device of claim 4 , wherein the overflow queue is shared by the N counters in the highest level in the hierarchy of levels.

10. The network device of claim 1 , wherein the N counters are stored in an on-chip SRAM memory, using the common memory pool.

11. A non-transitory computer-readable medium storing a mirrored shift logic and a hierarchy of levels of statistically multiplexed counters, wherein each level of the hierarchy of levels includes N counters arranged in rows having P base counters, and further wherein the mirrored shift logic extends the P base counters to a full width such that a full range of shifting is reduced.

12. The medium of claim 11 , wherein counters in the same row in one level of the hierarchy of levels are shuffled into different rows in a next level above of the hierarchy of levels.

13. The medium of claim 12 , wherein a randomization of the shuffle is a bit reverse of a counter identifier of a counter, a hash function or a bit arrangement in another order.

14. The medium of claim 11 , wherein the counter architecture is configured to update a counter by:
determining whether a corresponding row of the counter in a current level of the hierarchy of levels overflows;
based on the determination that the corresponding row in the current level does not overflow, processing each level below the current level by using a first routine and processing the current level by using a second routine; and
based on the determination that the corresponding row in the current level does overflow, determining whether a corresponding row of the counter in a next level above overflows;
based on the determination that the corresponding row of the counter in the next level above does not overflow, processing each level below the next level above by using the first routine and processing the next level above by using the second routine; and
based on the determination that the corresponding row of the counter in the next level above does overflow, when the next level above is not the highest level in the hierarchy of levels, returning to the step of determining whether a corresponding row of the counter in a next level above overflows, and when the next level above is the highest level in the hierarchy of levels, processing the next level above and each level below the next level above by using the first routine and updating an overflow queue.

15. The medium of claim 14 , wherein the first routine includes incrementing the counter in the corresponding level and shrinking the counter in the corresponding level.

16. The medium of claim 14 , wherein the second routine includes incrementing the counter in the corresponding level.

17. The medium of claim 16 , wherein the incrementing the counter includes expanding a size of the counter in the corresponding level.

18. The medium of claim 14 , wherein updating the overflow queue includes pushing a counter identifier of the counter and an overflow width into the overflow queue.

19. The medium of claim 14 , wherein the overflow queue is shared by the N counters in the highest level in the hierarchy of levels.

20. The medium of claim 11 , wherein the medium includes a static random access memory (SRAM) and the N counters are stored in the SRAM.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Wang Weihuang
• Schmidt Gerald
• Atluri Srinath
• Ma Weinan
• Lnu Shrikant Sundaram

Classifications

• H04L49/9084

  Reactions to storage capacity overflow · CPC title

• H04L47/62

  characterised by scheduling criteria · CPC title

• H03K21/10

  comprising logic circuits · CPC title

• H03K23/64

  with a base or radix other than a power of two (H03K23/40 - H03K23/62 take precedence) · CPC title

• H03K21/00

  Details of pulse counters or frequency dividers · CPC title