Signal development circuitry layouts in a memory device
US-12573436-B2 · Mar 10, 2026 · US
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Vimercati Daniele patents
Vimercati Daniele is listed as an inventor on 248 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Vimercati Daniele |
| Total patents | 248 |
| First publication | Jan 24, 2017 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Combinatory logic for multi-level memory cells
US-2026031135-A1 · Jan 29, 2026 · US
Differential latch sense amplifier
US-2026031134-A1 · Jan 29, 2026 · US
Multi-level memory cell read and writeback systems
US-2026031138-A1 · Jan 29, 2026 · US
Apparatuses and methods for providing memory device bleeder functionality
US-2025378873-A1 · Dec 11, 2025 · US
Memory cell sensing architecture
US-12494242-B2 · Dec 9, 2025 · US
Sense amplifier retention improvement
US-2025372146-A1 · Dec 4, 2025 · US
Silicon On Insulator Device with Floating Body Effect Mitigation
US-2025359033-A1 · Nov 20, 2025 · US
Memory device having conductive plate short repair
US-2025322898-A1 · Oct 16, 2025 · US
Negative feedback threshold compensation for sense amplifiers
US-2025279128-A1 · Sep 4, 2025 · US
Recent patents
Latest publications not already listed above.
Data invalidation for memory
US-2025274266-A1 · Aug 28, 2025 · US
Data masking for memory
US-12393354-B2 · Aug 19, 2025 · US
Enhanced sense amplifier architecture
US-2025261364-A1 · Aug 14, 2025 · US
VOLTAGE MANAGEMENT FOR IMPROVED tRP TIMING FOR FeRAM DEVICES
US-2025239287-A1 · Jul 24, 2025 · US
Storing bits with cells in a memory device
US-2025232819-A1 · Jul 17, 2025 · US
Voltage management for improved tRP timing for FeRAM devices
US-12293783-B2 · May 6, 2025 · US
Data invalidation for memory
US-12255984-B2 · Mar 18, 2025 · US
Storing bits with cells in a memory device
US-12237020-B2 · Feb 25, 2025 · US
PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES
US-2025054531-A1 · Feb 13, 2025 · US
Sense amplifier with digit line multiplexing
US-2025037756-A1 · Jan 30, 2025 · US
Data masking for memory
US-2024419338-A1 · Dec 19, 2024 · US
Adjusting a sensing voltage in memory
US-2024386933-A1 · Nov 21, 2024 · US
PMOS threshold compensation sense amplifier for FeRAM devices
US-12142311-B2 · Nov 12, 2024 · US
Memory array with multiplexed select lines and two transistor memory cells
US-12131766-B2 · Oct 29, 2024 · US
Memory array configuration for shared word lines
US-2024329840-A1 · Oct 3, 2024 · US
Sense amplifier with digit line multiplexing
US-12073870-B2 · Aug 27, 2024 · US
Memory cell sensing using two step word line enabling
US-12073864-B2 · Aug 27, 2024 · US
Thin film transistor deck selection in a memory device
US-12069847-B2 · Aug 20, 2024 · US
Thin film transistor deck selection in a memory device
US-2024276736-A1 · Aug 15, 2024 · US
Memory cell sensing architecture
US-2024257855-A1 · Aug 1, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 251 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/2273 | 209 |
| G11C11/221 | 204 |
| G11C11/2255 | 105 |
| G11C11/2275 | 91 |
| G11C11/2259 | 88 |