Thin film transistor deck selection in a memory device

Patent metadata

Field	Value
Publication number	US-12069847-B2
Application number	US-202318133929-A
Country	US
Kind code	B2
Filing date	Apr 12, 2023
Priority date	May 21, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

First claim

What is claimed is:

1. An apparatus, comprising:
a set of first memory cells of a memory die, the set of first memory cells associated with a first level above a substrate of the memory die;
a set of second memory cells of the memory die, the set of second memory cells associated with a second level above the substrate of the memory die;
a plurality of first access lines, each first access line of the plurality of first access lines coupled with a respective subset of the set of first memory cells and operable to couple with circuitry of a third level via a respective first transistor of a plurality of first transistors of the first level; and
a plurality of second access lines, each second access line of the plurality of second access lines coupled with a respective subset of the set of second memory cells and operable to couple with the circuitry of the third level via a respective second transistor of a plurality of second transistors of the first level.

2. The apparatus of claim 1 , wherein the first level is between the second level and the third level.

3. The apparatus of claim 1 , further comprising:
a plurality of conductors each coupled with a respective one of the plurality of first transistors, a respective one of the plurality of second transistors, and the circuitry associated with the third level.

4. The apparatus of claim 3 , wherein each conductor of the plurality of conductors is coupled with a decoder of the circuitry of the third level.

5. The apparatus of claim 1 , further comprising:
a plurality of third transistors of the first level each operable to couple a respective one of the plurality of first access lines with a respective one of the plurality of first transistors.

6. The apparatus of claim 1 , wherein:
each first transistor of the plurality of first transistors is associated with a respective first channel portion comprising one or more first semiconductor portions of the first level; and
each second transistor of the plurality of second transistors is associated with a respective second channel portion comprising one or more second semiconductor portions of the first level.

7. The apparatus of claim 6 , wherein:
each first memory cell of the set of first memory cells comprises a respective third transistor that is operable to couple a storage element of the first memory cell with a first access line of the plurality of first access lines, each respective third transistor associated with a respective third channel portion comprising one or more third semiconductor portions of the first level; and
each second memory cell of the set of second memory cells comprises a respective fourth transistor that is operable to couple a storage element of the second memory cell with a second access line of the plurality of second access lines, each respective fourth transistor associated with a respective fourth channel portion comprising one or more fourth semiconductor portions of the second level.

8. The apparatus of claim 7 , wherein:
the one or more first semiconductor portions, the one or more second semiconductor portions, and the one or more third semiconductor portions are overlapping along a height dimension relative to the substrate.

9. The apparatus of claim 6 , further comprising:
one or more first gate conductors of the first level each operable to modulate a conductivity of the respective first channel portions of each of the first transistors; and
one or more second gate conductors of the first level each operable to modulate a conductivity of the respective second channel portions of each of the second transistors.

10. The apparatus of claim 9 , wherein the one or more first gate conductors and the one or more second gate conductors are coupled with decoder circuitry of the third level.

11. The apparatus of claim 1 , wherein the circuitry associated with the third level comprises one or more transistors formed at least in part by a doped portion of the substrate.

12. A method, comprising:
identifying a row of first memory cells of a set of first memory cells of a memory die for an access operation, the memory die comprising the set of first memory cells in a first level above a substrate of the memory die and a set of second memory cells of the memory die in a second level above the substrate; and
coupling the row of first memory cells with circuitry associated with a third level based at least in part on the identifying, wherein coupling the row of first memory cells with the circuitry associated with the third level comprises:
coupling respective storage elements of the row of first memory cells with a set of access lines based at least in part on activating a plurality of first transistors of the first level; and
coupling the set of access lines with the circuitry associated with the third level based at least in part on activating a plurality of second transistors of the second level.

13. The method of claim 12 , further comprising:
isolating the set of second memory cells from the circuitry associated with the third level based at least in part on the identifying, wherein the isolating the set of second memory cells from the circuitry associated with the third level comprises:
isolating a set of second access lines from the circuitry associated with the third level based at least in part on deactivating a plurality of third transistors of the second level.

14. The method of claim 13 , further comprising:
coupling, based at least in part on the identifying and concurrently with coupling the respective storage elements of the row of first memory cells with the set of access lines, respective storage elements of a row of second memory cells of the set of second memory cells with the set of second access lines, the coupling based at least in part on activating a plurality of fourth transistors of the second level.

15. The method of claim 13 , further comprising:
coupling, based at least in part on enabling access of the memory die, the set of second access lines with the plurality of third transistors based at least in part on activating a plurality of fifth transistors of the second level.

16. An apparatus, comprising:
a set of first memory cells of a first level above a semiconductor substrate;
a set of second memory cells of a second level above the semiconductor substrate;
circuitry of a third level operable for accessing the set of first memory cells and the set of second memory cells; and
one or more processors configured to cause the apparatus to:
identify a row of first memory cells of the set of first memory cells for an access operation; and
couple the row of first memory cells with the circuitry of the third level based at least in part on the identifying, wherein coupling the row of first memory cells with the circuitry of the third level comprises:
coupling respective storage elements of the row of first memory cells with a set of access lines based at least in part on activating a plurality of first transistors of the first level; and
coupling the set of access lines with the circuitry of the third level based at least in part on activating a plurality of second transistors of the second level.

17. The apparatus of claim 16 , wherein the one or more processors are further configured to cause the apparatus to:
isolate the set of second memory cells from the circuitry of the third level based at least in part on the identifying, wherein the isolating the set of second memory cells from the circuitry of the third level comprises:
isolating a set of second access lines from the circuitry of

Assignees

• Micron Technology Inc

Inventors

• Vimercati Daniele

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title