Memory cell sensing architecture

Patent metadata

Field	Value
Publication number	US-12494242-B2
Application number	US-202418403498-A
Country	US
Kind code	B2
Filing date	Jan 3, 2024
Priority date	Jan 26, 2023
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Techniques and configurations for electronic memory are described. An apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. The apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. Also, a set of capacitors may be coupled with both nodes. The capacitors may support adjustment of the voltage of the nodes of the sense component.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first set of memory cells coupled with a first plate line and a word line, wherein a first memory cell of the first set of memory cells is coupled with a first bit line; a second set of memory cells coupled with a second plate line and the word line, wherein a first memory cell of the second set of memory cells is coupled with a second bit line; a sense component having a first node selectively couplable with the first bit line and having a second node selectively couplable with the second bit line; a first capacitor coupled with the first node of the sense component and a first voltage source, wherein the first voltage source is configured to adjust a voltage of the first node of the sense component via the first capacitor; a second capacitor coupled with the second node of the sense component and a second voltage source, wherein the second voltage source is configured to adjust a voltage of the second node of the sense component via the second capacitor; and a set of capacitors coupled with the first node of the sense component, the second node of the sense component, and a third voltage source, wherein the third voltage source is configured to concurrently adjust the voltage of the first node of the sense component and the voltage of the second node of the sense component via the set of capacitors.

2 . The apparatus of claim 1 , wherein:
a second memory cell of the first set of memory cells is coupled with the first plate line and a third bit line; and a second memory cell of the second set of memory cells is coupled with the second plate line and a fourth bit line.

3 . The apparatus of claim 2 , wherein:
the first node of the sense component is selectively couplable with the third bit line, and the second node of the sense component is selectively couplable with the fourth bit line.

4 . The apparatus of claim 1 , further comprising:
a first switch coupled with the first node of the sense component and the first bit line and configured to selectively couple the first node of the sense component with the first bit line; and a second switch coupled with the second node of the sense component and the second bit line and configured to selectively couple the second node of the sense component with the second bit line.

5 . The apparatus of claim 1 , further comprising:
a first switch coupled with the first bit line and configured to selectively couple the first bit line with a reference voltage; and a second switch coupled with the second bit line and configured to selectively couple the second bit line with the reference voltage.

6 . The apparatus of claim 1 , wherein:
the first set of memory cells comprises a first set of transistors and a first set of storage elements, the first set of transistors comprises a first transistor and a second transistor, and the first set of storage elements comprises a first storage element and a second storage element; the second set of memory cells comprises a second set of transistors and a second set of storage elements, the second set of transistors comprising a third transistor and a fourth transistor, and the second set of storage elements comprises a third storage element and a fourth storage element; a gate of the first transistor is coupled with the word line, a drain of the first transistor is coupled with the first bit line, and a source of the first transistor is coupled with a storage element of the first set of storage elements; and a gate of the third transistor is coupled with the word line, a drain of the third transistor is coupled with the second bit line, and a source of the third transistor is coupled with a storage element of the second set of storage elements.

7 . The apparatus of claim 1 , wherein:
the set of capacitors comprises a third capacitor and a fourth capacitor, a first node of the third capacitor is coupled with the first bit line and a second node of the third capacitor is coupled with the third voltage source, and a first node of the fourth capacitor is coupled with the first bit line and a second node of the fourth capacitor is coupled with the third voltage source.

8 . An apparatus, comprising:
a first set of memory cells coupled with a first plate line and a word line, wherein a first memory cell of the first set of memory cells is coupled with a first bit line; a second set of memory cells coupled with a second plate line and the word line, wherein a first memory cell of the second set of memory cells is coupled with a second bit line; a sense component having a latch circuit coupled between the first bit line and the second bit line; a set of capacitors coupled with a first control node, the first bit line, and the second bit line; a first capacitor coupled with a second control node and the first bit line; and a controller configured to:
adjust a voltage of the first control node coupled with the set of capacitors to concurrently adjust a voltage of the first bit line and a voltage of the second bit line;
activate the word line subsequent to adjusting the voltage of the first bit line and the voltage of the second bit line; and
adjust, subsequent to activating the word line, a voltage of the second control node coupled with the first capacitor to adjust the voltage of the first bit line.

9 . The apparatus of claim 8 , wherein a second memory cell of the first set of memory cells is coupled with a third bit line, and wherein, to access the first memory cell of the first set of memory cells, the controller is further configured to:
couple the third bit line to the first plate line prior to activating the word line; and adjust a voltage of the first plate line based at least in part on coupling the third bit line to the first plate line.

10 . The apparatus of claim 9 , further comprising:
a switch coupled with the first bit line and a reference voltage, wherein, to access the first memory cell of the first set of memory cells, the controller is further configured to:
isolate the first bit line from the reference voltage subsequent to adjusting the voltage of the first plate line.

11 . The apparatus of claim 9 , wherein, to access the first memory cell of the first set of memory cells, the controller is further configured to:
detect an offset voltage associated with the latch circuit, wherein the voltage of the first bit line and the voltage of the second bit line prior to adjusting the voltage of the first control node are configured to compensate for the offset voltage associated with the latch circuit.

12 . The apparatus of claim 9 , wherein:
the first memory cell of the first set of memory cells is configured to release charge to the first bit line based on the word line being activated and the voltage of the first plate line being adjusted, and the second memory cell of the first set of memory cells is configured to retain charge based on the third bit line being coupled to the first plate line.

13 . The apparatus of claim 11 , wherein the controller is further configured to:
adjust the voltage of the second control node coupled with the first capacitor after a duration since activating the word line has elapsed.

14 . The apparatus of claim 12 , wherein, to access the first memory cell of the first set of memory cells, the controller is further configured to:
activate, after the word line is activated and based on the voltage of the second control node coupled with the first capacitor being adjusted, the latch circuit to latch a logic stage based at least in part on a difference between the voltage of the first bit line and t

Assignees

• Micron Technology Inc

Inventors

• Vimercati Daniele
• Carman Eric

Classifications

• G11C5/10

  for interconnecting capacitors · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title