Memory cell sensing using two step word line enabling

Patent metadata

Field	Value
Publication number	US-12073864-B2
Application number	US-202217740528-A
Country	US
Kind code	B2
Filing date	May 10, 2022
Priority date	May 10, 2022
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

First claim

What is claimed is:

1. A method comprising:
maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell;
charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell; and
subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

2. The method of claim 1 , wherein the first operation comprises a sensing operation and wherein performing the sensing operation comprises setting a voltage on a third access line to a sensing voltage.

3. The method of claim 2 , wherein the sensing voltage is lower than the plate voltage by about a programming voltage.

4. The method of claim 2 , wherein the second access line comprises a word line for accessing a row of memory cells of a memory array.

5. The method of claim 2 , wherein the second operation comprises a programming operation.

6. The method of claim 5 , wherein the programming operation comprises setting a voltage on the third access line to a voltage equal to the plate voltage plus a programming voltage.

7. The method of claim 6 , wherein the second voltage is about equal to the plate voltage plus the first voltage plus the programming voltage.

8. A memory device, comprising:
an array of memory cells, the array comprised of a plurality of first access lines coupled to capacitive elements of respective memory cells of the array, a plurality of rows of memory cells coupled to respective second access lines, and a plurality columns of memory cells coupled to respective third access lines;
a plurality of selector devices coupled to the array such that at a gate of a selector device of the plurality of selector devices is coupled to a respective second access line of the array, a source of the selector device is coupled to a respective first access line, and a drain of the selector device is coupled to a respective third access line; and
a controller coupled to the array and configured to control selector devices to:
maintain a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell;
charge a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell; and
subsequent to the first operation, charge the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

9. The memory device of claim 8 , wherein a voltage drop across the selector device is less than or equal to three volts throughout the first operation and the second operation.

10. The memory device of claim 8 , wherein a leakage between second access lines and third access lines is less than about 10 nanoamps.

11. The memory device of claim 8 , wherein the first operation comprises a sensing operation and wherein the controller is configured to control the sensing operation by setting a voltage on a third access line to a sensing voltage.

12. The memory device of claim 11 , wherein the sensing voltage is lower than the plate voltage by about a programming voltage.

13. The memory device of claim 11 , wherein the second access line comprises a word line for accessing a row of memory cells of a memory array.

14. The memory device of claim 11 , wherein the second operation comprises a programming operation.

15. The memory device of claim 14 , wherein the controller is configured to control the programming operation by setting a voltage on the third access line to a voltage equal to the plate voltage plus a programming voltage.

16. The memory device of claim 15 , wherein the second voltage is about equal to the plate voltage plus the first voltage plus the programming voltage.

17. An apparatus comprising:
an array of memory cells, the array comprised of a plurality of first access lines coupled to capacitive elements of respective memory cells of the array, a plurality of rows of memory cells coupled to respective second access lines, and a plurality columns of memory cells coupled to respective third access lines; and
a sense component coupled to the array and configured to:
maintain a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell;
charge a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell; and
subsequent to the first operation, charge the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

18. The apparatus of claim 17 , wherein a leakage between second access lines and third access lines is less than about 10 nanoamps.

19. The apparatus of claim 17 , wherein the first operation comprises a sensing operation and wherein the sense component is configured to set a voltage on a third access line to a sensing voltage.

20. The apparatus of claim 19 , wherein the sensing voltage is lower than the plate voltage by about a programming voltage.

21. The apparatus of claim 19 , wherein the second access line comprises a word line for accessing a row of memory cells of a memory array.

22. The apparatus of claim 19 , wherein the second operation comprises a programming operation, and wherein the sense component is configured to set a voltage on the third access line to a voltage equal to the plate voltage plus a programming voltage during the programming operation.

23. The apparatus of claim 22 , wherein the second voltage is about equal to the plate voltage plus the first voltage plus the programming voltage.

Assignees

• Micron Technology Inc

Inventors

• Kitagawa Makoto
• Vimercati Daniele

Classifications

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title