Memory component timed by programmably-selected clock edge
US-12597454-B2 · Apr 7, 2026 · US
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Tsern Ely K patents
Tsern Ely K is listed as an inventor on 81 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Tsern Ely K |
| Total patents | 81 |
| First publication | Feb 12, 2015 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory component with adjustable core-to-interface data rate ratio
US-2025054525-A1 · Feb 13, 2025 · US
Memory controller with error detection and retry modes of operation
US-2025004867-A1 · Jan 2, 2025 · US
Memory component with adjustable core-to-interface data rate ratio
US-12094565-B2 · Sep 17, 2024 · US
Memories and memory components with interconnected and redundant data interfaces
US-2024257863-A1 · Aug 1, 2024 · US
Memory controller supporting nonvolatile physical memory
US-2024241824-A1 · Jul 18, 2024 · US
Memory controller with error detection and retry modes of operation
US-12026038-B2 · Jul 2, 2024 · US
Memories and memory components with interconnected and redundant data interfaces
US-11955165-B2 · Apr 9, 2024 · US
Memory Controller With Error Detection And Retry Modes Of Operation
US-2024070000-A1 · Feb 29, 2024 · US
Memory controller supporting nonvolatile physical memory
US-11914508-B2 · Feb 27, 2024 · US
Recent patents
Latest publications not already listed above.
Memory controller with error detection and retry modes of operation
US-11775369-B2 · Oct 3, 2023 · US
Memories and memory components with interconnected and redundant data interfaces
US-2022148643-A1 · May 12, 2022 · US
Memories and memory components with interconnected and redundant data interfaces
US-11211114-B2 · Dec 28, 2021 · US
Memory component with adjustable core-to-interface data rate ratio
US-2021280226-A1 · Sep 9, 2021 · US
Memory component with pattern register circuitry to provide data patterns for calibration
US-2021098048-A1 · Apr 1, 2021 · US
Process for Making a Semiconductor System
US-2021098280-A1 · Apr 1, 2021 · US
Memory component with adjustable core-to-interface data rate ratio
US-10964361-B2 · Mar 30, 2021 · US
Memory controller supporting nonvolatile physical memory
US-2021073122-A1 · Mar 11, 2021 · US
Memory controller
US-2021027825-A1 · Jan 28, 2021 · US
Memory control component with inter-rank skew tolerance
US-2020349991-A1 · Nov 5, 2020 · US
Memory controller supporting nonvolatile physical memory
US-10817419-B2 · Oct 27, 2020 · US
Memory component with pattern register circuitry to provide data patterns for calibration
US-10811080-B2 · Oct 20, 2020 · US
Semiconductor system
US-10804139-B2 · Oct 13, 2020 · US
Memory Controller With Error Detection And Retry Modes Of Operation
US-2020264943-A1 · Aug 20, 2020 · US
Memory controller
US-10706910-B2 · Jul 7, 2020 · US
Memory component with multiple command/address sampling modes
US-10650872-B2 · May 12, 2020 · US
Memory controller with error detection and retry modes of operation
US-10621023-B2 · Apr 14, 2020 · US
Memories and memory components with interconnected and redundant data interfaces
US-2019378560-A1 · Dec 12, 2019 · US
Memory controller
US-2019325936-A1 · Oct 24, 2019 · US
Memories and memory components with interconnected and redundant data interfaces
US-10360972-B2 · Jul 23, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Rambus Inc | 81 |
| Ware Frederick A | 2 |
| Tsern Ely K | 2 |
| Hampel Craig E | 1 |
| Horowitz Mark A | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C7/10 | 35 |
| G11C7/1072 | 32 |
| G11C11/4076 | 31 |
| G06F3/0673 | 28 |
| G11C7/1066 | 25 |