Memory controller with error detection and retry modes of operation

Patent metadata

Field	Value
Publication number	US-12026038-B2
Application number	US-202318449118-A
Country	US
Kind code	B2
Filing date	Aug 14, 2023
Priority date	Jun 3, 2005
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) system comprising:
DRAM integrated circuits; and
a memory controller to issue write commands to the DRAM integrated circuits;
wherein each one of the DRAM integrated circuits comprises circuitry to:
receive, from the memory controller, for one of the write commands which seeks to access the one of the DRAM integrated circuits, corresponding write data and a corresponding error detection code; and
determine whether there is an error in the one of the write commands, as received by the one of the DRAM integrated circuits;
responsive to determination that there is an error in the one of the write commands, as received by the one of the DRAM integrated circuits, prevent a write operation corresponding to the write command from being completed, and also transfer information, to the memory controller, representing the determination that there is an error in the one of the write commands, as received by the one of the DRAM integrated circuits;
calculate, from the corresponding write data, as received by the one of the DRAM integrated circuits, write data error information; and
responsive to determination that there no error in the one of the write commands, access a DRAM storage array of the one of the DRAM integrated circuits to store information, dependent on the corresponding write data, in the DRAM storage array.

2. The DRAM system of claim 1 wherein:
for the one of the write commands, the corresponding error detection code is dependent on the corresponding write data, as well a memory address designated by the one of the write commands;
the circuitry is further to determine whether there is an error in the corresponding write data, as received by the one of the DRAM integrated circuits; and
responsive to the determination that there is an error in the corresponding write data, as received by the one of the DRAM integrated circuits, the circuitry is to correct the corresponding write data, such that the information stored in the DRAM storage array comprises an error-corrected version of the corresponding write data.

3. The DRAM system of claim 2 wherein the error detection code comprises a cyclic redundancy code (CRC), and wherein the circuitry is to correct the corresponding write data using the CRC.

4. The DRAM system of claim 1 wherein:
the corresponding error detection code is dependent on the corresponding write data, as well a memory address designated by the corresponding one of the write commands; and
the circuitry is further to transfer the error information, to the memory controller.

5. The DRAM system of claim 4 wherein the memory controller comprises circuitry to re-issue the one of the write commands, to the one of the DRAM integrated circuits which is to be accessed by the one of the write commands, in response to a determination based on the error information that the write data has an error.

6. The DRAM system of claim 4 wherein the circuitry to transfer the error information to the memory controller is to do so in a manner that is not solicited by a request from the memory controller.

7. The DRAM system of claim 4 wherein the circuitry to transfer the error information to the memory controller is to do so using a link which is not used for exchange, with the memory controller, of write data or read data.

8. The DRAM system of claim 1 wherein the circuitry is to transfer, to the memory controller, the information representing the determination that there is an error, in the one of the write commands, in a manner that is not solicited by a request from the memory controller.

9. The DRAM system of claim 1 wherein the error detection code comprises parity information.

10. The DRAM system of claim 1 wherein the memory controller comprises a serializer, wherein the circuitry of each of the DRAM integrated circuits comprises a deserializer, and wherein the circuitry of the one of the DRAM integrated circuits is to deserialize the one of the write commands, using the deserializer of the one of the DRAM integrated circuits, to generate deserialized information, and is to determine whether there is an error in the one of the write commands using the deserialized information.

11. The DRAM system of claim 1 wherein:
the circuitry comprises a buffer to queue the corresponding write data for a predetermined period of time; and
the circuitry is further to, in absence of determination that there is error in the one of the write commands, store the corresponding write data, as received by the one of the DRAM integrated circuits, in the DRAM storage array.

12. The DRAM system of claim 11 wherein:
the buffer is also to queue a memory address corresponding to the one of the write commands;
the circuitry is further to receive a read command, subsequent to receipt of the one of the write commands, where the read command specifies the memory address; and
the circuitry is to service the read command, when the read command is received within the predetermined period of time following receipt of the one of the write commands, by retrieving the corresponding write data from the buffer and by transmitting the data retrieved from the buffer to the memory controller.

13. The DRAM system of claim 1 wherein the memory controller comprises circuitry to:
buffer the one of the write commands, for at least a predetermined period of time, following issuance of the one of the write commands; and
receive, from the one of the DRAM integrated circuits which is to be accessed by the one of the write commands, the information representing the determination that there is an error in the one of the write commands, and responsively perform a remedial retry action, in which the one of the write commands is re-issued to the one of the DRAM integrated circuits which is to be accessed by the one of the write commands.

14. The DRAM system of claim 13 wherein the circuitry of the memory controller is to re-issue the one of the write commands using at least one of a greater voltage, a slower signal transmission rate, error correction information, or a different symbol transmission format.

15. The DRAM system of claim 1 , wherein the one of the write commands comprises a first field and a second field, and wherein the error detection code identifies the existence of the error in the first field, only, but does not permit correction of the error in the first field.

16. The DRAM system of claim 1 wherein:
the memory controller is also to issue read commands, to the one of the DRAM integrated circuits which is to be accessed by the one of the write commands, each read command together with a corresponding error detection code; and
the circuitry is further to:
receive the read commands and the error detection codes corresponding to the read commands, and determine whether there is an error in a given one of the read commands; and
responsive to a determination that there is an error in the given one of the read commands, mask a read operation, corresponding to the given one of the read commands, from being completed.

17. The DRAM system of claim 1 wherein:
the memory controller is also to issue read commands, to the one of the DRAM integrated circuits which is to be accessed by the one of the write commands, each read command together with a corresponding error detection code; and
the circuitry is further to:
receive the read commands and the error detection codes corresponding to the read commands, and determine whether there is an error in a given one of the read commands; and
responsive to a determination that

Assignees

• Rambus Inc

Inventors

• Tsern Ely K
• Horowitz Mark A
• Ware Frederick A

Classifications

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title