Memories and memory components with interconnected and redundant data interfaces

Patent metadata

Field	Value
Publication number	US-11955165-B2
Application number	US-202117532745-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Mar 10, 2015
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

First claim

What is claimed is:

1. A memory module comprising:
a module substrate having a first module data port, a second module data port, and a third module data port;
first and second memory components each having redundant and interconnected first and second memory-component data interfaces with respective first and second memory-component data ports;
a first memory-component substrate having a first signal trace extending from the first module data port through the first memory-component substrate, a second signal trace extending between the second module data port and the first memory-component data port of the first memory component, the second signal trace forming a first point-to-point connection from the second module data port to the first memory-component data port of the first memory component, and a third signal trace extending between the third module data port and the second memory-component data port of the first memory component; and
a second memory-component substrate having a fourth signal trace extending between the first signal trace of the first memory-component substrate and the first memory-component data port of the second memory component, the first and fourth signal traces forming a second point-to-point connection from the first module data port to the first memory-component data port of the second memory component, and a fifth signal trace extending between the third signal trace of the first memory-component substrate and the second memory-component data port of the second memory component.

2. The memory module of claim 1 , further comprising a first connection ball between the first memory-component substrate and the first memory component, the first connection ball electrically connecting the third signal trace to the second memory- component data port of the first memory component.

3. The memory module of claim 2 , further comprising a second connection ball between the first memory-component substrate and the second memory- component substrate, the second connection ball electrically connecting the third signal trace of the first memory-component substrate to the fifth signal trace of the second memory-component substrate.

4. The memory module of claim 3 , wherein the second connection ball is larger than the first connection ball.

5. The memory module of claim 1 , wherein the first memory-component substrate includes a first surface facing the module substrate and a second surface facing the first memory component, the first surface including a first substrate pad electrically connected to the first module data port, a second substrate pad electrically connected to the second module data port, and a third substrate pad electrically connected to the third module data port.

6. The memory module of claim 5 , the second surface of the first memory-component substrate including a fourth substrate pad across from the second substrate pad, offset from the first substrate pad, and electrically connected to the first substrate pad via the first signal trace; a fifth substrate pad offset from the second substrate pad and electrically connected to the second substrate pad via the second signal trace; a sixth substrate pad offset from the third substrate pad and electrically connected to the third substrate pad via the third signal trace; and a seventh substrate pad across from and electrically connected to the third substrate pad.

7. The memory module of claim 6 , wherein the second memory-component substrate includes a third surface facing the first memory component and a fourth surface facing the second memory component, the third surface including a first substrate pad electrically connected to the first module data port via the first signal trace and a second substrate pad electrically connected to the third module data port via the third signal trace.

8. The memory module of claim 1 , wherein at least one of the first memory component and the second memory component includes DRAM memory.

9. The memory module of claim 1 , the first memory component including a first command port and the second memory component including a second command port communicatively coupled to the first command port.

10. A memory module comprising:
a module substrate having a first module data port, a second module data port, and a third module data port;
first and second memory components each having a first memory-component data port and a second memory-component data port;
a first memory-component substrate having a first signal trace extending from the first module data port through the first memory-component substrate, a second signal trace extending between the second module data port and the first memory-component data port of the first memory component, and a third signal trace extending between the third module data port and the second memory-component data port of the first memory component; and
a second memory-component substrate having a fourth signal trace extending between the first signal trace of the first memory-component substrate and the first memory-component data port of the second memory component, and a fifth signal trace extending between the third signal trace of the first memory-component substrate and the second memory-component data port of the second memory component;
wherein the module substrate includes a first module-substrate side bearing the first, second, and third module data ports and a second module-substrate side bearing a fourth module data port, a fifth module data port, and a sixth module data port;
third and fourth memory components each having a first memory-component data port and a second memory-component data port;
a third memory-component substrate having a first signal trace extending from the fourth module data port through the third memory-component substrate, a second signal trace extending between the fifth module data port and the first memory-component data port of the third memory component, and a third signal trace extending between the sixth module data port and the second memory-component data port of the third memory component; and
a fourth memory-component substrate having a fourth signal trace extending between the first signal trace of the third memory-component substrate and the first memory-component data port of the fourth memory component, and a fifth signal trace extending between the third signal trace of the third memory-component substrate and the second memory-component data port of the fourth memory component.

11. The memory module of claim 10 , the module substrate including a module trace electrically connecting the third signal trace of the first memory-component substrate to the third signal trace of the third memory-component substrate.

12. The memory module of claim 11 , further comprising a module connector coupled to the second signal trace of the first memory-component substrate.

13. A memory package comprising:
a first sub-package including:
a first memory component having redundant and interconnected first and second memory-component data interfaces with respective first and second memory-component data ports; and
a first memory-component substrate having a first signal trace extending through the first memory-component substrate, a second signal trace extending through the first memory-component substrate to the first memory-component data port of the first memory component, the second signal trace forming a first point-to-point connection to the first memory-component data port of the first memory component, and a third signal trace extending through the first memory-component substrate to the second memory-component data port of the first memory component; and

a second sub-pack

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely K
• Linstadt John E
• Giovannini Thomas A
• Best Scott C
• Wright Kenneth L

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title