Memory controller with error detection and retry modes of operation

Patent metadata

Field	Value
Publication number	US-11775369-B2
Application number	US-202016805619-A
Country	US
Kind code	B2
Filing date	Feb 28, 2020
Priority date	Jun 3, 2005
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

First claim

What is claimed is:

1. A memory device, embodied as an integrated circuit, the memory device comprising:
at least one memory array;
interface circuitry to receive, from a memory controller, write commands, associated data, information with which to detect an error in the write commands, and error correction codes to correct an error in the associated data;
array control circuitry to, in fulfilment of the write commands, detect and correct errors in the associated data using the error correction codes and to write the associated data into the at least one memory array; and
command error detection circuitry to detect existence of error in at least one of the write commands in dependence on the information, and to prevent the writing of the data associated with the at least one of the write commands into the at least one memory array upon detection of the error in the at least one of the write commands.

2. The memory device of claim 1 , wherein each array of the at least one memory array comprises one or more arrays of dynamic random access memory (DRAM) cells.

3. The memory device of claim 1 , wherein the memory device further comprises circuitry to communicate information identifying the existence of the error in the at least one of the write commands to the memory controller.

4. The memory device of claim 3 , wherein the circuitry to communicate the information identifying the existence of the error in the at least one of the write commands is to do so unsolicitedly, via a link not used for exchange of write data or read data with the memory controller.

5. The memory device of claim 1 , wherein the information is parity information.

6. The memory device of claim 1 , wherein the error correction code is a cyclic code.

7. The memory device of claim 6 , wherein:
the associated data is to be transferred over a serial communication link;
the memory device further comprises a deserializer to deserialize the associated data, to generate deserialized data; and
the array control circuitry is to correct error in the deserialized data, prior to the write of data into the at least one memory array.

8. The memory device of claim 1 , further comprising a deserializer, wherein the memory device is to deserialize the command with the deserializer, to generate deserialized information, and is to detect the existence of the error in the at least one of the write commands from the deserialized information.

9. The memory device of claim 1 , wherein:
the memory device comprises a buffer to queue the write commands for a predetermined period of time corresponding to an integer number of symbol transmission periods; and
the array control circuitry, in absence of detection of error in the write commands by the error detection circuitry, is to write the associated data into the at least one memory array for the queued write commands.

10. The memory device of claim 9 , wherein the array control circuitry is to service data from the buffer in fulfilment of a read command directed to data which is in the buffer.

11. The memory device of claim 1 , wherein each of the write commands comprises first fields and second fields, and wherein the information identifies the existence of the error in the first fields only but does not permit correction of the error in the first fields.

12. A memory device embodied as an integrated circuit, the memory device, comprising:
at least one dynamic random access memory (DRAM) array;
interface circuitry to receive, from a memory controller, write commands, associated data, information with which to detect an error in the commands, and error correction codes to correct an error in the associated data;
array control circuitry to, in fulfilment of the write commands, detect and correct errors in the associated data using the error correction codes and to write the associated data into the at least one DRAM array; and
command error detection circuitry to detect existence of error in one or more of the write commands and to cause the memory device to ignore each erroneous write command in dependence on the information, so as to prevent the writing of the associated data into the at least one DRAM array.

13. The memory device of claim 12 , wherein the memory device further comprises circuitry to communicate information identifying the existence of the error in one or more of the write commands to the memory controller and to communicate information identifying the existence of an error in the associated data to the memory controller.

14. The memory device of claim 13 , wherein the circuitry to communicate the information identifying the existence of the error in the associated data is to do so unsolicitedly, via a link not used for exchange of write data or read data with the memory controller.

15. The memory device of claim 12 , wherein the information identifying the existence of error in the one or more of the write commands is parity information.

16. The memory device of claim 12 , wherein the error correction code is a cyclic code.

17. The memory device of claim 16 , wherein:
the associated data is to be transferred over a serial communication link;
the memory device further comprises a deserializer to deserialize the associated data, to generate deserialized data; and
the array control circuitry is to correct error in the deserialized data, prior to the write of data into the at least one memory array.

18. The memory device of claim 12 , further comprising a deserializer, wherein the memory device is to deserialize the command with the deserializer, to generate deserialized information, and is to detect the existence of the error in the one or more of the write commands from the deserialized information.

19. The memory device of claim 12 , wherein:
the memory device comprises a buffer to queue the write commands for a predetermined period of time, comprising an integer number of symbol transmission periods; and
the array control circuitry, in absence of detection of error in the write commands by the error detection circuitry, is to write the associated data into the at least one DRAM array for the queued write commands.

20. The memory device of claim 19 , wherein the array control circuitry is to service data from the buffer in fulfilment of a read command directed to data which is in the buffer.

21. The memory device of claim 12 , wherein each of the write commands comprises first fields and second fields, and wherein the information identifies the existence of the error in the first fields only but does not permit correction of the error in the first fields.

22. A memory device, embodied as an integrated circuit, the memory device comprising:
at least one dynamic random access memory (DRAM) array;
interface circuitry to receive, from a memory controller, write commands, associated data, first information with which to detect an error in the commands, and second information with which to detect an error in the data;
array control circuitry to, in fulfilment of the write commands, write the associated data into the at least one DRAM array; and
command error detection circuitry to detect existence of error in one or more of the write commands and to cause the memory device to ignore each erroneous command in dependence on the respective first information, so as to prevent the writing of the associated data into the at least one DRAM array;
wherein the associated data is to be transferred over a serial communication link and the memory device further c

Assignees

• Rambus Inc

Inventors

• Tsern Ely K
• Horowitz Mark A
• Ware Frederick A

Classifications

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F11/006

  Identification (G06F11/2289 takes precedence) · CPC title