Virtual management unit scheme for two-pass programming in a memory sub-system

Patent metadata

Field	Value
Publication number	US-11922011-B2
Application number	US-202117464442-A
Country	US
Kind code	B2
Filing date	Sep 1, 2021
Priority date	Sep 1, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address. The mapping is updated to associate the set of virtual MUs with the second physical address.

First claim

What is claimed is:

1. A method comprising:
responsive to receiving a request from a host system to program a data item to one or more memory devices, performing one or more operations to program the data item to a first set of physical management units (MUs) associated with a first portion of one or more memory devices of a memory sub-system and a second set of physical MUs associated with a second portion of the one or more memory devices, wherein the first portion comprises memory cells of a first type and the second portion comprises memory cells of a second type, wherein the first set of physical MUs is associated with a first physical address of the one or more memory devices, and wherein the second set of physical MUs is associated with a second physical address of the one or more memory devices;
generating, in a virtual MU data structure, a mapping that associates the first physical address of the one or more memory devices with a set of virtual MUs associated with the one or more memory devices, wherein the set of virtual MUs correspond to one or more block stripes of the memory sub-system;
adding an entry associated with the data item to a logical-to-physical (L2P) table associated with the one or more memory devices, wherein the entry comprises an identifier associated with the set of virtual MUs;
detecting that programming the data item to the second set of physical MUs by the one or more operations is completed; and
responsive to the detecting, updating the mapping of the virtual MU data structure to associate the set of virtual MUs with the second physical address.

2. The method of claim 1 , further comprising:
determining that the set of virtual MUs is available for allocation to the data item; and
updating a first field of an entry to the virtual MU data structure to include the mapping between the set of virtual MUs and the first physical address.

3. The method of claim 2 , wherein updating the mapping to associate the set of virtual MUs with the second physical address comprises:
updating the first field of the entry of the virtual MU data structure to include the mapping between the set of virtual MUs and the second physical address.

4. The method of claim 3 , wherein the entry of the virtual MU data structure further comprises a second field that includes an indication of whether the data item is programmed to memory cells of the first type or memory cells of the second type, and wherein the method further comprises:
responsive to adding the entry to the virtual MU data structure, setting the second field of the entry to indicate that the data item is programmed to memory cells of the first type; and
responsive to updating the first field of the entry of the virtual MU data structure to include the mapping between the set of virtual MU and the second physical address, updating the second field of the entry to indicate that the data item is programmed to memory cells of the second type.

5. The method of claim 1 , further comprising:
programming the data item to the second set of physical MUs in accordance with a first pass programming operation of a two-pass programming scheme associated with the memory device, and wherein detecting that the data item is programmed to the second set of physical MUs comprises determining that a second pass programming operation of the two-pass programming scheme is complete.

6. The method of claim 5 , further comprising:
responsive to detecting that the data item is programmed to the second set of physical MUs in accordance with the first pass programming operation, updating an entry of a memory conversion data structure to include a mapping associating the first set of physical MUs with the second set of physical MUs and the set of virtual MUs.

7. The method of claim 6 , further comprising:
responsive to detecting that the data item is programmed to the second set of physical MUs, erasing the entry of the memory conversion data structure.

8. The method of claim 1 , wherein the memory cells of the first type comprise single level cells (SLCs) and the memory cells of the second type comprise at least one or more of multi-level cells (MLCs), triple-level cells (TLCs) or quadruple-level cells (QLCs).

9. A system comprising
one or more memory devices; and
a processing device coupled to each of the one or more memory devices, the processing device to perform operations comprising:
receiving a request to perform a memory access operation to access a data item stored at the one or more memory devices, wherein the memory access operation comprises at least one of a read operation or a write operation;
responsive to identifying, in a logical-to-physical (L2P) table associated with the one or more memory devices, an entry that corresponds a logical address associated with the data item of the received request, obtaining an identifier for a set of virtual management units (MUs) associated with the one or more memory devices from the identified entry, wherein the set of virtual MUs correspond to one or more block stripes across the one or more memory devices;
identifying, in a virtual MU data structure, a record mapping the set of virtual MUs to a physical address associated with a portion of the one or more memory devices that stores the data item of the received request; and
performing the memory access operation using the physical address to access the data item stored at the one or more memory devices in accordance with the request.

10. The system of claim 9 , wherein identifying the record mapping the set of virtual MUs to the physical address associated with a portion of the one or more memory devices that stores the data item of the received request comprises:
determining that an entry of the virtual MU data structure includes the mapping between at least the set of virtual MUs and a set of physical MUs of the one or more memory devices that stores the data item; and
extracting the physical address from the entry of the virtual MU data structure.

11. The system of claim 10 , wherein the entry of the virtual MU data structure comprises an indication of whether the data item is programmed to memory cells of a first type or memory cells of a second type, and wherein the memory access operation is performed to access the data item at the physical address in view of the indication.

12. The system of claim 11 , wherein the memory cells of the first type comprise single level cells (SLCs) and the memory cells of the second type comprise at least one or multi-level cells (MLCs), triple-level cells (TLCs) or quadruple-level cells (QLCs).

13. The system of claim 9 , wherein the one or more memory devices comprise a first portion and a second portion, the first portion comprising memory cells associated with a first type and the second portion comprising memory cells of a second type, and wherein the request to perform the memory access operation is received before a completion of a process to program the data item to a set of physical MUs associated with the second portion of the memory device.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
responsive to receiving a request from a host system to program a data item to one or more memory devices, performing one or more operations to program the data item to a first set of physical management units (MUs) associated with a first portion of one or more memory devices of a memory sub-system and a second set of physical MUs associated with a second portion of the one or more memory devices, wherein the

Assignees

• Micron Technology Inc

Inventors

• Lam Johnny A
• Mudugal Samyukta
• Subbarao Sanjay
• Harris Byron D
• Boals Daniel A

Classifications

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title