Caching of logical-to-physical mapping information in a memory sub-system

Patent metadata

Field	Value
Publication number	US-12130748-B2
Application number	US-202318225958-A
Country	US
Kind code	B2
Filing date	Jul 25, 2023
Priority date	Mar 16, 2021
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:
receiving a request specifying a logical address associated with a host-initiated operation directed at a first portion of the memory device; and
providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;
the secondary FTL configured to perform operations comprising:
accessing, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
determining an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table;
identifying, based on a chunk in a read cache corresponding to a chunk address determined based an entry number of the entry in the read cache table, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device; and
providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.

2. The system of claim 1 , wherein the operations further comprise determining the chunk address by adding the logical address to a result of multiplying the entry number by a size of the chunk.

3. The system of claim 2 , wherein the size of the chunk corresponds to an indirection size of the L2P table.

4. The system of claim 1 , wherein:
the L2P table is a first L2P table; and
the second portion of the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.

5. The system of claim 4 , wherein:
the request is a first request;
the logical address is a first logical address;
the host-initiated operation is a first host-initiated operation;
the entry is a first entry; and
the operations further comprise:
receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device;
identifying a second entry in the first L2P table that corresponds to the second logical address;
accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and
adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.

6. The system of claim 5 , wherein the operations further comprise:
adding a new entry to the read cache table corresponding to the accessed portion of the first L2P table added to the read cache.

7. The system of claim 6 , wherein adding the new entry to the read cache table comprises:
randomly selecting an existing entry in the read cache table; and
replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

8. The system of claim 5 , wherein the operations further comprise:
identifying, based on the first L2P table, a physical location within the second portion of the memory device that corresponds to the portion of the second L2P table that specifies a second physical address within the first portion of the memory device that corresponds to the second logical address; and
identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device that corresponds to the second logical address specified by the second request; and
performing the second host-initiated operation at the second physical address within the first portion of the memory device.

9. The system of claim 1 , wherein:
the memory device is a NAND memory device;
the first portion comprises multiple quad-level cells (QLCs); and
the second portion comprises multiple single level cells (SLCs).

10. The system of claim 1 , wherein the host-initiated operation comprises one of:
a read operation, a write operation, or an erase operation.

11. The system of claim 1 , wherein the volatile memory component comprises one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).

12. A method comprising:
receiving, by a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device;
providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address;
accessing, by the secondary FTL, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
determining an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table,
identifying, by the secondary FTL, a physical address that corresponds to the logical address specified by the request based on a chunk in a read cache corresponding to a chunk address determined based on an entry number of the entry in the read cache table, the physical address corresponding to a physical location in the first portion of memory device;
providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and
performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.

13. The method of claim 12 , further comprising determining the chunk address by adding the logical address to a result of multiplying the entry number by a size of the chunk.

14. The method of claim 13 , wherein the size of the chunk corresponds to an indirection size of the L2P table.

15. The method of claim 12 , wherein:
the L2P table is a first L2P table; and
the second portion of the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.

16. The method of claim 15 , wherein:
the request is a first request;
the logical address is a first logical address;
the host-initiated operation is a first host-initiated operation;
the entry is a first entry; and
the operations further comprise:
receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device;
identifying a second entry in the first L2P table that corresponds to the second logical address;
accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and
adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.

17. T

Assignees

• Micron Technology Inc

Inventors

• Subbarao Sanjay

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/1048

  Scalability · CPC title

• G06F2212/283

  Plural cache memories · CPC title