Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits

Patent metadata

Field	Value
Publication number	US-11289495-B1
Application number	US-202017038037-A
Country	US
Kind code	B1
Filing date	Sep 30, 2020
Priority date	Sep 30, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

First claim

What is claimed is:

1. A memory bit cell circuit comprising:
a substrate;
a first plurality of fins extending in a first direction on the substrate, wherein a smallest center-to-center distance from a first fin to a nearest adjacent fin of the first plurality of fins, in a second direction orthogonal to the first direction, is a minimum fin pitch;
a storage circuit configured to store a data value, the storage circuit comprising a storage circuit active area of the substrate, the storage circuit active area comprising a first subset of the first plurality of fins;
a read port circuit configured to read the data value, the read port circuit comprising a read port active area of the substrate; the read port active area comprising a second subset of the first plurality of fins; and
an inactive area between the storage circuit active area and the read port active area,
wherein a width of the inactive area in the second direction from the storage circuit active area to the read port active area is between 1.0 and 2.15 times the minimum fin pitch.

2. The memory bit cell circuit of claim 1 , wherein the width of the inactive area is between forty five (45) nanometers (nm) and fifty five (55) nm.

3. The memory bit cell circuit of claim 1 , wherein the smallest center-to-center distance from the first fin to the nearest adjacent fin is a predetermined distance.

4. The memory bit cell circuit of claim 1 , wherein the storage circuit further comprises:
a write access Fin Field-Effect Transistor (FET) (FinFET) configured to supply the data value to the storage circuit, the write access FinFET comprising a first gate; and
a first gate contact vertically coupled to the first gate, the first gate contact comprising an area in a vertical interconnect layer disposed above the first gate,
wherein at least a portion of the area of the first gate contact overlaps the storage circuit active area.

5. The memory bit cell circuit of claim 4 , wherein an entire area of the first gate contact is above the storage circuit active area.

6. The memory hit cell circuit of claim 1 , wherein the inactive area comprises a non-diffusion region.

7. The memory bit cell circuit of claim 1 , wherein the inactive area comprises at least one inactive fin.

8. The memory bit cell circuit of claim 1 ; wherein:
the storage circuit is configured to store a true data value and a complement data value;
the read port circuit comprises a first read port circuit configured to read the complement data value;
the first read port circuit comprises a first read port active area of the substrate disposed on a first end of the storage circuit in the second direction; and
the memory bit cell circuit further comprises a second read port circuit configured to read the true data value, the second read port circuit comprising a second read port active area of the substrate on a second end of the storage circuit in the second direction, the second read port active area comprising a third subset of the first plurality of fins.

9. The memory bit cell circuit of claim 1 , wherein:
the storage circuit active area comprises one or more of a P-type diffusion region and an N-type diffusion region; and
the read port active area comprises one or more of a P-type diffusion region and an N-type diffusion region.

10. The memory bit cell circuit of claim 1 , wherein:
the storage circuit comprises a six-transistor (6T) static random access memory (SRAM) bit cell circuit; and
the read port circuit comprises a two-transistor (2T) read port circuit.

11. A memory bit cell array circuit comprising:
a substrate;
a first memory bit cell circuit comprising:
a first plurality of fins extending in a first direction on the substrate, wherein a smallest center-to-center distance from a first fin to a nearest adjacent fin of the first plurality of fins, in a second direction orthogonal to the first direction, is a minimum fin pitch;
a first storage circuit configured to store a first data value, the first storage circuit comprising a first storage circuit active area of the substrate, the first storage circuit active area comprising a first subset of the first plurality of fins; and
a first read port circuit configured to read the first data value, the first read port circuit comprising a first read port active area of the substrate, the first read port active area comprising a second subset of the first plurality of fins,
wherein the first read port circuit is on a first side of the first storage circuit in the second direction;

a second memory bit cell circuit comprising:
a second plurality of fins extending in the first direction on the substrate;
a second storage circuit configured to store a second data value, the second storage circuit comprising a second storage circuit active area of the substrate, the second storage circuit active area comprising a first subset of the second plurality of fins; and
a second read port circuit configured to read the second data value, the second read port circuit comprising a second read port active area of the substrate, the second read port active area comprising a second subset of the second plurality of fins,
wherein the second read port circuit is on a second side of the second storage circuit in the second direction; and

an inactive array area between the first read port circuit and the second read port circuit, wherein a width of the inactive array area from the first read port active area to the second read port active area is between 1.0 and 2.15 times the minimum fin pitch.

12. The memory bit cell array circuit of claim 11 , wherein:
the first memory bit cell circuit further comprises a first inactive bit cell area between the first read port active area and the first storage circuit active area;
a width of the first inactive bit cell area in the second direction is between 1.0 and 2.15 times the minimum fin pitch;
the second memory bit cell circuit further comprises a second inactive bit cell area between the second read port active area and the second storage circuit active area; and
a width of the second inactive bit cell area in the second direction is between 1.0 and 2.15 times the minimum fin pitch.

13. The memory bit cell array circuit of claim 11 , wherein:
the first memory bit cell circuit further comprises a first write access Fin Field-Effect Transistor (FET) (FinFET) configured to supply the first data value to the first storage circuit, the first write access FinFET comprising a first gate;
a first gate contact is vertically coupled to the first gate, the first gate contact comprising a first area in a vertical interconnect layer disposed above the first gate; and
at least a portion of the first area of the first gate contact overlaps the first storage circuit active area.

14. The memory bit cell array circuit of claim 13 , wherein:
the second memory bit cell circuit further comprises a second write access FinFET configured to supply the second data value to the second storage circuit, the second write access FinFET comprising a second gate;
a second gate contact is vertically coupled to the second gate, the second gate contact comprising a second area in a vertical interconnect layer disposed above the second gate; and
at least a portion of the second area of the second gate contact overlaps the second storage circuit active area.

15. The memory bit cell array circuit of claim 14 , wherein
the first area of the first gate contact is entirely overlapping the first storage circuit active area; and
the second area of the second gate contact is entirely overlapping the second storage ci

Assignees

• Qualcomm Inc

Inventors

• Biradar Rahul
• Sharma Sunil
• Desai Channappa
• Ghosh Sonia

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D89/10

  Integrated device layouts · CPC title