Static random-access memory (SRAM) array circuits including bilateral well tap cells with reduced width folded finger structure

Patent metadata

Field	Value
Publication number	US-11469239-B1
Application number	US-202117217067-A
Country	US
Kind code	B1
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

First claim

What is claimed is:

1. A static random-access memory (SRAM) array circuit, comprising:
a substrate;
a plurality of rows of SRAM bit cell circuits disposed on the substrate, each of the plurality of rows extending in a first axis direction;
a plurality of columns of the SRAM bit cell circuits, the plurality of columns extending in a second axis direction orthogonal to the first axis direction; and
a column of well tap cells disposed between a first column of the plurality of columns and a second column of the plurality of columns, the column of well tap cells comprising a well tap cell disposed in each row of the plurality of rows;
wherein:
the substrate comprises a P-type substrate;
the well tap cell in each row comprises an N-well in the P-type substrate, the N-well extending in the first axis direction;
the N-well of the well tap cell in a first row of the plurality of rows is separated from the N-well of the well tap cell in a second row of the plurality of rows by the P-type substrate; and
a P-type well tap is disposed in the P-type substrate between the N-well of the well tap cell in the first row and the N-well of the well tap cell in the second row and provides ground voltage to the SRAM bit cell circuits on a first side of the column of well tap cells and to the SRAM bit cell circuits on a second side of the column of well tap cells.

2. The SRAM array circuit of claim 1 , the well tap cell in the first row further comprising an N-type well tap disposed in the N-well of the well tap cell in the first row providing a supply voltage to the SRAM bit cell circuits on the first side of the column of well tap cells and to the SRAM bit cell circuits on the second side of the column of well tap cells.

3. The SRAM array circuit of claim 2 , wherein each well tap cell further comprises:
a P-type implant region extending in the second axis direction; and
an N-type implant region extending in the second axis direction;
wherein:
the P-type well tap is disposed in the P-type implant region; and
the N-type well tap is disposed in the N-type implant region.

4. The SRAM array circuit of claim 2 , wherein the P-type well tap comprises:
a plurality of P-ties on the P-type substrate, each P-tie comprising a first source/drain region on a first side of a gate region and a second source/drain region on a second side of the gate region, the first source/drain region electrically coupled to the second source/drain region.

5. The SRAM array circuit of claim 4 , wherein the first source/drain region, the second source/drain region, and the gate region in each of the plurality of P-ties comprise regions of a fin on the P-type substrate.

6. The SRAM array circuit of claim 4 , wherein the P-type well tap further comprises:
a first folded finger comprising a first portion of a first metal layer coupled to the first source/drain regions of a first plurality of P-ties;
a second folded finger comprising a second portion of the first metal layer coupled to the second source/drain regions of the first plurality of P-ties; and
a second metal layer electrically coupled to the first folded finger and the second folded finger.

7. The SRAM array circuit of claim 6 , wherein the P-type well tap further comprises:
a third folded finger comprising a third portion of the first metal layer;
the second source/drain regions of the first plurality of P-ties comprise the first source/drain regions of a second plurality of P-ties; and
the third folded finger is coupled to the second source/drain regions of the second plurality of P-ties.

8. The SRAM array circuit of claim 4 , wherein the P-type well tap comprises eight (8) P-ties.

9. The SRAM array circuit of claim 4 , wherein the P-type well tap comprises sixteen (16) P-ties.

10. The SRAM array circuit of claim 4 , wherein the N-type well tap of the well tap cell in the first row comprises:
a plurality of N-ties on the N-well, each N-tie comprising a first source/drain region on a first side of a gate region and a second source/drain region on a second side of the gate region, the first source/drain region electrically coupled to the second source/drain region.

11. The SRAM array circuit of claim 10 , wherein the N-type well tap comprises eight (8) N-ties.

12. The SRAM array circuit of claim 3 , each well tap cell further comprising:
fins extending in the first axis direction; and
a middle fin cut extending in the second axis direction, the middle fin cut comprising a fin gap between the fins in the P-type implant region and the fins in the N-type implant region.

13. The SRAM array circuit of claim 12 , each well tap cell further comprising:
a first side bit cell termination between the first column of the plurality of columns of the SRAM bit cell circuits and the P-type implant region;
a first side fin cut between the first side bit cell termination and the P-type implant region, the first side fin cut comprising a fin gap between the fins in the first side bit cell termination and the fins in the P-type implant region;
a second side bit cell termination between the second column of the plurality of columns of the SRAM bit cell circuits and the N-type implant region; and
a second side fin cut between the second side bit cell termination and the N-type implant region, the second side fin cut comprising a fin gap between the fins in the second side bit cell termination and the fins in the N-type implant region.

14. The SRAM array circuit of claim 12 , further comprising gates extending above the fins in the second axis direction and spaced apart at a gate pitch in the first axis direction;
wherein:
the column of well tap cells is between a first SRAM bit cell circuit in the first column of the plurality of columns and a second SRAM bit cell circuit in the second column of the plurality of columns; and
a width of the column of well tap cells is equal to fourteen (14) times the gate pitch in the first axis direction.

15. The SRAM array circuit of claim 1 , integrated into a radio-frequency (RF) front end module.

16. The SRAM array circuit of claim 1 integrated into a device selected from the group consisting of a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

17. An integrated circuit (IC) comprising a static random-access memory (SRAM) array circuit, the SRAM array circuit comprising:
a substrate;
a plurality of rows of SRAM bit cell circuits disposed on the substrate, each of the plurality of rows extending in a first axis direction;
a plurality of columns of the SRAM bit cell circuits, the plurality of columns extending in a second axis direction orthogonal to the first axis direction; and
a column of well tap cells disposed between a first column of the plurality of columns and a second column of the plurality of columns, the column of well tap cells comprising a well tap cell disposed in ea

Assignees

• Qualcomm Inc

Inventors

• Desai Channappa
• Sharma Sunil
• Srikanth Anne
• Kodlipet Pradeep Jayadev
• Gao Yandong

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• G11C11/414 Primary

  for memory cells of the bipolar type · CPC title

• H01L27/0928

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L27/1104 Primary

  Electricity · mapped topic