Erase operation for non-volatile memory cell
US-2026094648-A1 · Apr 2, 2026 · US
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Nguyen Kha patents
Nguyen Kha is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nguyen Kha |
| Total patents | 28 |
| First publication | Jul 4, 2019 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Input circuitry for analog neural memory in a deep learning artificial neural network
US-12579422-B2 · Mar 17, 2026 · US
Resistive random access memory cell array
US-2025342883-A1 · Nov 6, 2025 · US
Row decoder and row address scheme in a memory system
US-12380932-B2 · Aug 5, 2025 · US
Vector-by-matrix mutiplication array comprising control gate lines perpendicular to word lines
US-2025174271-A1 · May 29, 2025 · US
Neural network device
US-12248870-B2 · Mar 11, 2025 · US
Read and programming decoding system for analog neural memory
US-12237011-B2 · Feb 25, 2025 · US
Row decoder and row address scheme in a memory system
US-2024339136-A1 · Oct 10, 2024 · US
Decoders for analog neural memory in deep learning artificial neural network
US-12099921-B2 · Sep 24, 2024 · US
Transceiver for providing high voltages for erase or program operations in a non-volatile memory system
US-12062397-B2 · Aug 13, 2024 · US
Recent patents
Latest publications not already listed above.
Redundancy for an array of non-volatile memory cells using tag registers
US-2024256146-A1 · Aug 1, 2024 · US
Word line driver for vector-by-matrix multiplication array
US-2024095508-A1 · Mar 21, 2024 · US
Transceiver for providing high voltages for erase or program operations in a non-volatile memory system
US-2023141943-A1 · May 11, 2023 · US
Input circuitry for analog neural memory in a deep learning artificial neural network
US-2023048411-A1 · Feb 16, 2023 · US
Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in deep learning artificial neural network
US-11568229-B2 · Jan 31, 2023 · US
Read and programming decoding system for analog neural memory
US-2023018166-A1 · Jan 19, 2023 · US
Decoding system and physical layout for analog neural memory in deep learning artificial neural network
US-11423979-B2 · Aug 23, 2022 · US
Programmable neuron for analog non-volatile memory in deep learning artificial neural network
US-11354562-B2 · Jun 7, 2022 · US
Decoders for analog neural memory in deep learning artificial neural network
US-2021342682-A1 · Nov 4, 2021 · US
Charge pump for use in non-volatile flash memory devices
US-11120881-B2 · Sep 14, 2021 · US
Decoders for analog neural memory in deep learning artificial neural network
US-11087207-B2 · Aug 10, 2021 · US
Charge pump for use in non-volatile flash memory devices
US-2021035643-A1 · Feb 4, 2021 · US
Charge pump for use in non-volatile flash memory devices
US-10847227-B2 · Nov 24, 2020 · US
Decoding system and physical layout for analog neural memory in deep learning artificial neural network
US-2020342938-A1 · Oct 29, 2020 · US
Charge Pump For Use In Non-volatile Flash Memory Devices
US-2020118632-A1 · Apr 16, 2020 · US
Redundant Memory Access For Rows Or Columns Containing Faulty Memory Cells In Analog Neural Memory In Deep Learning Artificial Neural Network
US-2020019849-A1 · Jan 16, 2020 · US
Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network
US-2019286976-A1 · Sep 19, 2019 · US
Programmable Neuron For Analog Non-Volatile Memory In Deep Learning Artificial Neural Network
US-2019205729-A1 · Jul 4, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Silicon Storage Tech Inc | 28 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/0425 | 21 |
| G11C11/54 | 18 |
| G06N3/065 | 17 |
| G06N3/0464 | 15 |
| G06F17/16 | 15 |