Transceiver for providing high voltages for erase or program operations in a non-volatile memory system

Patent metadata

Field	Value
Publication number	US-2023141943-A1
Application number	US-202217585261-A
Country	US
Kind code	A1
Filing date	Jan 26, 2022
Priority date	Nov 8, 2021
Publication date	May 11, 2023
Grant date	—

Abstract

Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

First claim

What is claimed is:

1 . A transceiver for a non-volatile memory system, comprising:
a PMOS transistor comprising a first terminal coupled to a first node, a second terminal, and a gate; and a native NMOS transistor comprising a first terminal coupled to the second terminal of the PMOS transistor, a second terminal coupled to a second node, and a gate; wherein the transceiver can provide a first high voltage on one of the first node and the second node in response to receiving a second high voltage on the other of the first node and the second node.

2 . The transceiver of claim 1 , wherein the gate of the PMOS transistor receives a voltage smaller in magnitude than the first high voltage.

3 . The transceiver of claim 1 , wherein the output signal of the transceiver is coupled to the non-volatile memory system for use in erase or program operations of the non-volatile memory system.

4 . The transceiver of claim 1 , wherein the gate of the native NMOS transistor is connected to ground when the transceiver is disabled.

5 . The transceiver of claim 1 , further comprising a charge pump.

6 . The transceiver of claim 1 , further comprising a second PMOS transistor and a second native NMOS transistor forming a circuit path between the first node and the second node.

7 . A transceiver for a non-volatile memory, comprising:
a PMOS transistor comprising a first terminal, a second terminal, and a gate; an NMOS transistor comprising a first terminal coupled to the first terminal of the PMOS transistor coupled to a first node, a second terminal, and a gate; and a native NMOS transistor comprising a first terminal coupled to the second terminal of the PMOS transistor and the second terminal of the NMOS transistor, a second terminal coupled to a second node, and a gate; wherein the transceiver selectively provides a first high voltage on one of the first node and the second node in response to receiving a second high voltage on the other of the first node and the second node.

8 . The transceiver of claim 7 , wherein the first high voltage is used during erase or program operations in the flash memory.

9 . The transceiver of claim 7 , wherein the gate of the PMOS transistor receives a voltage smaller in magnitude than the first high voltage.

10 . The transceiver of claim 7 , wherein the gate of the native NMOS transistor is connected to ground when the transceiver is disabled.

11 . The transceiver of claim 7 , further comprising a charge pump.

12 . The transceiver of claim 7 , further comprising a second PMOS transistor and a second native NMOS transistor forming a circuit path.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Ly Anh
• Nguyen Kha
• Pham Hien
• Nguyen Duc

Classifications

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C16/0425

  comprising cells containing a merged floating gate and select transistor · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title