Neural network device

Patent metadata

Field	Value
Publication number	US-12248870-B2
Application number	US-202318520500-A
Country	US
Kind code	B2
Filing date	Nov 27, 2023
Priority date	Mar 14, 2018
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

First claim

What is claimed is:

1. A neural network device, comprising:
a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first gate disposed over and insulated from a second portion of the channel region, a second gate disposed over and insulated from the floating gate, and a third gate disposed over and insulated from the source region;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate; and
the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first gates in one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the second gates in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the third gates in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the source regions in one of the rows of the memory cells; and
a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells; and

wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of second lines or on the plurality of fifth lines, and to provide the first plurality of outputs as electrical currents on the plurality of fourth lines.

2. The neural network device of claim 1 , wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of second lines.

3. The neural network device of claim 1 , wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of fifth lines.

4. The neural network device of claim 1 , comprising a first plurality of neurons configured to receive the first plurality of outputs.

5. The neural network device of claim 4 , comprising a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises:
a plurality of second memory cells, wherein each of the second memory cells includes spaced apart second source and second drain regions formed in the semiconductor substrate with a second channel region extending there between, a second floating gate disposed over and insulated from a first portion of the second channel region, a fourth gate disposed over and insulated from a second portion of the second channel region, a fifth gate disposed over and insulated from the second floating gate, and a sixth gate disposed over and insulated from the second source region;
wherein each of the plurality of second memory cells is configured to store a second weight value corresponding to a number of electrons on the second floating gate and the plurality of second memory cells are configured generate the second plurality of outputs based upon the second plurality of inputs and the stored second weight values;

wherein the second memory cells of the second plurality of synapses are arranged in rows and columns, and wherein the second plurality of synapses comprises:
a plurality of sixth lines each electrically connecting together the fourth gates in one of the rows of the second memory cells;
a plurality of seventh lines each electrically connecting together the fifth gates in one of the columns of the second memory cells;
a plurality of eighth lines each electrically connecting together the sixth gates in one of the rows of the second memory cells;
a plurality of ninth lines each electrically connecting together the second source regions in one of the rows of the second memory cells; and
a plurality of tenth lines each electrically connecting together the second drain regions in one of the columns of the second memory cells; and

wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of seventh lines or on the plurality of tenth lines, and to provide the second plurality of outputs as electrical currents on the plurality of ninth lines.

6. The neural network device of claim 5 , wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of seventh lines.

7. The neural network device of claim 5 , wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of tenth lines.

8. The neural network device of claim 5 , further comprising a second plurality of neurons configured to receive the second plurality of outputs.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Hong Stanley
• Ly Anh
• Vu Thuan
• Pham Hien
• Nguyen Kha
• Tran Han

Classifications

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G11C2216/04

  Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title