Apparatuses and methods for semiconductor devices including clock signal lines

Patent metadata

Field	Value
Publication number	US-11264068-B2
Application number	US-202017122801-A
Country	US
Kind code	B2
Filing date	Dec 15, 2020
Priority date	Oct 2, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.

First claim

What is claimed is:

1. An apparatus comprising a chip including:
a first side and a second side extending in a first direction;
a center region disposed between the first and second sides;
a side region disposed between the center region and the first side;
a first clock driver disposed in the center region;
a second clock driver disposed in the center region;
a third clock driver disposed in the side region;
a first clock signal line including:
a first wiring segment extending in the center region and coupled to the first clock driver and configured to provide a first plurality of clock signals from the first clock driver; and

a second clock signal line including:
a second wiring segment extending from the center region to the side region and coupled to the second clock driver and further coupled to the third clock driver, and configured to provide a second plurality of clock signals from the second clock driver to the third clock driver.

2. The apparatus of claim 1 , wherein the chip is a memory core chip comprising a plurality of data queue (DQ) core cells configured to receive or provide data, and
wherein the second clock signal line further comprises a third wiring segment coupled to the third clock driver and extending to the plurality of DQ core cells.

3. The apparatus of claim 1 , wherein the first clock driver is configured to drive the first plurality of clock signals and the second clock driver is configured to drive the second plurality of clock signals different from the first plurality of clock signals.

4. The apparatus of claim 3 , further comprising a fourth clock driver disposed in the center region and coupled to the first wiring segment,
wherein the chip is a memory core chip comprising a plurality of data queue (DQ) core cells configured to receive or provide data, and
wherein the first clock signal line further comprises:
a fourth wiring segment coupled to the fourth clock driver and extending to the plurality of DQ core cells.

5. The apparatus of claim 3 , wherein the chip is a memory core chip, and
wherein the second plurality of clock signals include at least one of a write clock signal or a read clock signal.

6. The apparatus of claim 5 , further comprising:
an interface chip; and
one or more vias, each via configured to interconnect the interface chip and the memory core chip,
wherein the first clock driver is configured to receive the first plurality of clock signals from the interface chip through the vias, and further configured to drive the first wiring segment.

7. The apparatus of claim 6 , wherein the interface chip comprises a third wiring segment extending in the first direction and configured to provide the first plurality of clock signals.

8. The apparatus of claim 5 , wherein the first plurality of clock signals include one or more first pointer signals.

9. The apparatus of claim 8 , wherein the chip further comprises:
a third wiring segment extending in the center region; and
a pointer driver disposed in the center region and coupled to the third wiring segment, and configured to drive one or more second pointer signals different from the one or more first pointer signals.

10. An apparatus comprising a chip including:
a first side and a second side extending in a first direction;
a center region disposed between the first and second sides;
a side region disposed between the center region and the first side;
a first driver disposed in the center region;
a second driver disposed in the center region;
a third driver disposed in the side region;
a first signal line including:
a first wiring segment extending in the center region and coupled to the first driver; and

a second signal line including:
a second wiring segment extending from the center region to the side region and coupled to the second driver and further coupled to the third driver, and configured to provide one or more clock signals from the second driver to the third driver.

11. The apparatus of claim 10 , wherein the first driver is configured to drive one or more pointer signals.

12. The apparatus of claim 11 , wherein the second driver is configured to drive the one or more clock signals.

13. The apparatus of claim 12 , further comprising:
a fourth driver disposed in the center region;
a fifth driver disposed in the side region; and
a third signal line including:
a third wiring segment extending from the center region to the side region and coupled to the fourth clock driver and further coupled to the fifth clock driver.

14. The apparatus of claim 13 , further comprising an interface chip configured to provide one or more via clock signals,
wherein the fourth driver is configured to receive the one or more via clock signals.

15. The apparatus of claim 14 , wherein the interface chip comprises:
a third side and a fourth side extending in a first direction;
a first region disposed between the third and fourth sides;
a second region disposed between the first region and the third side;
a fourth wiring segment extending from the first region to the second region;
a sixth driver disposed in the center region and coupled to the fourth wiring segment, and configured to drive the one or more via clock signals; and
a seventh driver disposed in the side region and coupled to the fourth wiring segment.

16. An apparatus comprising one or more memory core chips, wherein each memory core chip of the one or more memory core chips comprises:
a first side and a second side extending in a first direction;
a center region disposed between the first and second sides;
a side region disposed between the center region and the first side;
a first clock driver disposed in the center region and configured to drive one or more first clock signals;
a second clock driver disposed in the center region and configured to drive one or more second clock signals;
a third clock driver disposed in the side region and configured to drive the one or more second clock signals;
a first clock signal line including:
a first wiring segment extending in the center region and coupled to the first clock driver, and

a second clock signal line including:
a second wiring segment coupled to the second clock driver and the third clock driver, and configured to provide the one or more second clock signals from the second clock driver to the third clock driver.

17. The apparatus of claim 16 , further comprising:
an interface chip configured to receive a clock signal from a memory controller and further configured to provide one or more clock signals; and
one or more vias configured to receive the one or more clock signals from the interface chip and further configured to provide the one or more clock signals to the one or more memory core chips,
wherein the first clock driver is configured to receive the one or more via clock signals and further configured to drive the one or more via clock signals as the one or more first clock signals.

18. The apparatus of claim 17 , wherein the interface chip comprises:
a fourth clock driver configured to drive the one or more via clock signals; and
a third wiring segment extending in the first direction and coupled to the fourth clock driver.

19. The apparatus of claim 16 , further comprising:
an interface chip configured to receive a clock signal from a memory controller and further configured to provide one or more via clock signals; and
one or more vias configured to receive the one or more via clock signals from the interface chip and further co

Assignees

• Micron Technology Inc

Inventors

• Yatsushiro Ryosuke
• Narui Seiji

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/07254

  changes in dispositions · CPC title