Semiconductor layered device with data bus inversion

Patent metadata

Field	Value
Publication number	US-10664432-B2
Application number	US-201815987895-A
Country	US
Kind code	B2
Filing date	May 23, 2018
Priority date	May 23, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

First claim

What is claimed is:

1. An apparatus comprising:
a data bus inversion (DBI) circuit configured to receive a string of input data including first input data, second input data following the first input data and third input data following the second input data, and further configured to provide a string of output data including first output data, second output data following the first output data and third output data following the second output data, which are either with or without data bus inversion, the DBI circuit including:
a first circuit configured to temporarily latch the first input data and further configured to latch the third input data;
a second circuit configured to temporarily latch the second input data;
a first DBI calculator circuit configured to perform first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and
a second DBI calculator circuit configured to perform second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

2. The apparatus of claim 1 , wherein the first circuit comprises a first flip-flop (FF) circuit and a second FF circuit coupled in series;
wherein the first FF circuit is configured to store the first input data,
wherein the second FF circuit is configured to store the first input data responsive to the second circuit latching the second input data, and
wherein the first FF circuit is configured to store the third input data.

3. The apparatus of claim 2 , wherein the first DBI calculator circuit is coupled to the second FF circuit and further coupled to the second circuit, and
wherein the second DBI calculator circuit is coupled to the first FF circuit and further coupled to the second circuit.

4. The apparatus of claim 1 , wherein the first circuit comprises a plurality of first first-in first-out (FIFO) circuits and a plurality of second FIFO circuits,
wherein the second circuit comprises a plurality of third FIFO circuits, and
wherein the plurality of first FIFO circuits, the plurality of second FIFO circuits and the plurality of third FIFO circuits are coupled to an input data bus that is configured to transmit the string of input data in order to temporarily latch the first, third and second input data, respectively.

5. The apparatus of claim 4 , wherein the first DBI calculator circuit is configured to be coupled to the first FIFO circuits and further configured to be coupled to the plurality of third FIFO circuits; and
wherein the second DBI calculator circuit is configured to be coupled to the second FIFO circuits and further configured to be coupled to the third FIFO circuits.

6. An apparatus comprising:
a first plurality of FIFO circuits configured to receive at least a first portion of a plurality of corresponding bits of data and a first pointer signal, and further configured to provide a plurality of corresponding bits of first latched data responsive to the first pointer signal;
a second plurality of FIFO circuits configured to receive at least a second portion of the plurality of corresponding bits of data and a second pointer signal, and further configured to provide a plurality of corresponding bits of second latched data responsive to the second pointer signal;
a DBI calculator configured to receive the plurality of corresponding bits of the first latched data and the plurality of corresponding bits of the second latched data and further configured to provide a current DBI calculation result signal after a DBI calculation cycle,
wherein each FIFO circuit of the first plurality of FIFO circuits includes:
an input circuit configured to receive a corresponding bit of the data and the first pointer signal, and further configured to latch the corresponding bit of the data responsive to the first pointer signal to provide a corresponding bit of the first latched data;
a bit inverter configured to receive the corresponding bit of the first latched data and the current DBI calculation result signal, and configured to provide the corresponding bit of the first latched data with or without inversion as a bit inverter output signal responsive to the current DBI calculation result signal; and
a logic circuit coupled to the bit inverter, and configured to provide the bit inverter output signal responsive to a delayed first pointer signal that has a delay of a DBI calculation cycle with reference to the first pointer signal.

7. The apparatus of claim 6 , further comprising a plurality of pre-DBI latch circuits configured to receive the plurality of corresponding bits of the second latched data and further configured to provide the plurality of corresponding bits of the second latched data responsive to the first pointer signal,
wherein the DBI calculator is configured to receive the plurality of corresponding bits of the second latched data from the plurality of pre-DBI latch circuits responsive to the first pointer signal.

8. The apparatus of claim 6 , wherein the input circuit in each FIFO circuit of the first plurality of FIFO circuits is a first FF circuit, and
wherein the logic circuit includes:
a second FF circuit configured to latch the bit inverter output signal responsive to the delayed first pointer signal; and
a NAND circuit configured to provide the bit inverter output signal responsive to the delayed first pointer signal in an active state.

9. The apparatus of claim 6 , wherein the logic circuit includes a NAND circuit configured to provide the bit inverter output signal responsive to the delayed first pointer signal in an active state, and
wherein the delayed first pointer signal is the second pointer signal.

10. The apparatus of claim 6 , further comprising an input data bus configured to transmit the plurality of corresponding bits of data including the first portion of the plurality of corresponding bits of data and the second portion of the plurality of corresponding bits of data,
wherein the first plurality of FIFO circuits are configured to receive the at least the first portion of the plurality of corresponding bits of data from the input data bus, and
wherein the second plurality of FIFO circuits are configured to receive the at least the second portion of the plurality of corresponding bits of data from the input data bus.

11. The apparatus of claim 6 , further comprising:
a first input data bus configured to transmit the plurality of corresponding bits of data including the first portion of the plurality of corresponding bits of data; and
a second input data bus configured to transmit the second portion of the plurality of corresponding bits of data,
wherein the first plurality of FIFO circuits are configured to receive the at least the first portion of the plurality of corresponding bits of data from the first input data bus, and
wherein the second plurality of FIFO circuits are configured to receive the at least the second portion of the plurality of corresponding bits of data from the second input data bus.

12. The apparatus of claim 11 , further comprising a serializer circuit configured to receive the plurality of corresponding bits of first latched data with or without inversion and the plurality of corresponding bits of the second latched data with or without inversion, and further configured to provide the plurality of corresponding bits of first latched data with or without inversion and the plurality of corresponding bits of second latched data with or without inversion alternatingly in series responsive to a clock sig

Assignees

• Micron Technology Inc

Inventors

• Ebihara Yuki
• Narui Seiji

Classifications

• G11C11/4023

  using field effect transistors · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F13/4265 Primary

  on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title