Memory failure prediction and mitigation
US-2026079801-A1 · Mar 19, 2026 · US
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Lim Su Wei patents
Lim Su Wei is listed as an inventor on 81 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lim Su Wei |
| Total patents | 81 |
| First publication | Apr 30, 2015 |
| Latest publication | Mar 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Locked raid memory devices
US-2026023644-A1 · Jan 22, 2026 · US
Root complex integrated endpoint emulation of a discreet pcie endpoint
US-2026023713-A1 · Jan 22, 2026 · US
Memory compression with improved lookup table scheme
US-2026016956-A1 · Jan 15, 2026 · US
Memory failure prediction and mitigation
US-12511205-B2 · Dec 30, 2025 · US
Retrieving user data and cyclic redundancy check information using a single access operation
US-2025390377-A1 · Dec 25, 2025 · US
Root complex integrated endpoint emulation of a discreet PCIE endpoint
US-12455850-B2 · Oct 28, 2025 · US
Memory compression with improved lookup table scheme
US-12449974-B2 · Oct 21, 2025 · US
Systems and methods for communicating encrypted time-related data
US-12452223-B2 · Oct 21, 2025 · US
Interface techniques for stacked memory architectures
US-2025279133-A2 · Sep 4, 2025 · US
Recent patents
Latest publications not already listed above.
Memory compression with improved lookup table scheme
US-2025085851-A1 · Mar 13, 2025 · US
Memory failure prediction and mitigation
US-2024403177-A1 · Dec 5, 2024 · US
Interface techniques for stacked memory architectures
US-2024404581-A1 · Dec 5, 2024 · US
System, apparatus and method for synchronizing multiple virtual link states over a package interconnect
US-12001353-B2 · Jun 4, 2024 · US
Virtualized link states of multiple protocol layer package interconnects
US-11663154-B2 · May 30, 2023 · US
System, Apparatus And Method For Synchronizing Multiple Virtual Link States Over A Package Interconnect
US-2023026906-A1 · Jan 26, 2023 · US
Hardware mechanisms for link encryption
US-11533170-B2 · Dec 20, 2022 · US
Virtualized link states of multiple protocol layer package interconnects
US-2022350769-A1 · Nov 3, 2022 · US
System, apparatus and method for synchronizing multiple virtual link states over a package interconnect
US-11442876-B2 · Sep 13, 2022 · US
Dynamic provisioning of pcie devices at run time for bare metal servers
US-2022156211-A1 · May 19, 2022 · US
Virtualized link states of multiple protocol layer package interconnects
US-11308018-B2 · Apr 19, 2022 · US
Reduced pin count interface
US-11163717-B2 · Nov 2, 2021 · US
Method, apparatus, and system for power management on a CPU die via clock request messaging protocol
US-11016549-B2 · May 25, 2021 · US
Reduced pin count interface
US-2021056067-A1 · Feb 25, 2021 · US
Virtualized link states of multiple protocol layer package interconnects
US-2020409899-A1 · Dec 31, 2020 · US
Virtualized link states of multiple protocol layer package interconnects
US-10776302-B2 · Sep 15, 2020 · US
Reduced pin count interface
US-10706003-B2 · Jul 7, 2020 · US
Reduced pin count interface
US-2019303338-A1 · Oct 3, 2019 · US
Hardware mechanisms for link encryption
US-2019229901-A1 · Jul 25, 2019 · US
Virtualized link states of multiple protocol layer package interconnects
US-2019227972-A1 · Jul 25, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 68 |
| Micron Technology Inc | 10 |
| Lim Su Wei | 7 |
| Teoh Poh Thiam | 5 |
| Yeem Kah Meng | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F13/4282 | 37 |
| Y02D10/00 | 25 |
| G06F13/4221 | 22 |
| G06F13/4068 | 22 |
| G06F11/1004 | 19 |