Method, apparatus, and system for power management on a CPU die via clock request messaging protocol

Patent metadata

Field	Value
Publication number	US-11016549-B2
Application number	US-201815870629-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jan 12, 2018
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

First claim

What is claimed is:

1. A method for managing power of a connected device, the method comprising:
transmitting, from a central processing unit (CPU) root port, to a platform controller hub (PCH) compliant with a Peripheral Component Interconnect Express (PCIe) protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH;
detecting that a connected device is entering into a power management state; and
transmitting, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

2. The method of claim 1 , wherein the second bit of the second clock request message comprises an asserted clock request no sample protocol bit for a power management state that does not require clock request sampling.

3. The method of claim 2 , further comprising:
transmitting, from the CPU to the PCH a third clock request message, the third clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH and a second bit set to deassert the clock request no sample protocol.

4. The method of claim 1 , wherein the second bit of the second clock request message comprises an asserted clock request sample protocol bit for a power management state that uses clock request sampling.

5. The method of claim 4 , further comprising, for a deasserted 3.3 volt GPIO pin, performing power management of a connected device.

6. The method of claim 5 , wherein the CPU receives a clock request message receive state assert_b/deassert_b message indicating that the 3.3 volt GPIO pin is deasserted.

7. The method of claim 4 , wherein the power management state comprises a detect state for a hot plug protocol.

8. The method of claim 1 , wherein the CPU is in an L1.0 power management state, and wherein the second bit of the second clock request message comprises an asserted bit to start an L1.1 protocol.

9. The method of claim 8 , further comprising:
receiving from the PCH a clock request message; and
entering into an L1.1 state from the L1.0 state.

10. The method of claim 1 , further comprising:
determining that an attached device supports an L1.2 power management state; and
wherein the second bit of the second clock request message comprises a start/end L1.2 protocol bit set, and the second clock request message further comprising a third bit indicating a Tpower_on Scale and a fourth bit indicating a Power On Wait Time bit.

11. A computing system comprising:
a central processing unit (CPU); and
a root port complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the root port complex local to and connected to the CPU, the root port complex to:
transmit to a platform controller hub (PCH) compliant with a Peripheral Component Interconnect Express (PCIe) protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH;
detect that a connected device is entering into a power management state; and
transmit to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

12. The computing system of claim 11 , wherein the second bit of the second clock request message comprises an asserted clock request no sample protocol bit for a power management state that does not require clock request sampling.

13. The computing system of claim 12 , the root port complex to:
transmit, from the CPU to the PCH a third clock request message, the third clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH and a second bit set to deassert the clock request no sample protocol.

14. The computing system of claim 11 , wherein the second bit of the second clock request message comprises an asserted clock request sample protocol bit for a power management state that uses clock request sampling.

15. The computing system of claim 14 , the root port complex to, for a deasserted 3.3 volt GPIO pin, perform power management of a connected device.

16. The computing system of claim 15 , wherein the root port complex receives a clock request message receive state assert_b/deassert_b message indicating that the 3.3 volt GPIO pin is deasserted.

17. The computing system of claim 14 , wherein the power management state comprises a detect state for a hot plug protocol.

18. The computing system of claim 11 , wherein the CPU is in an L1.0 power management state, and wherein the second bit of the second clock request message comprises an asserted bit to start an L1.1 protocol.

19. The computing system of claim 18 , the root port complex to:
receive from the PCH a clock request message; and
enter into an L1.1 state from the L1.0 state.

20. The computing system of claim 11 , the root port complex to:
determine that an attached device supports an L1.2 power management state; and
wherein the second bit of the second clock request message comprises a start/end L1.2 protocol bit set, and the second clock request message further comprising a third bit indicating a Tpower_on Scale and a fourth bit indicating a Power On Wait Time bit.

21. A platform controller hub (PCH) compliant with a Peripheral Component Interconnect Express (PCIe) protocol coupled to the root port complex across a sideband network, the PCH comprising a general purpose input/output (GPIO) circuit comprising a 3.3 volt pin; the PCH comprising logic to:
cause the 3.3 volt pin of the GPIO circuit to enter into an asserted state;
receive, from a central processing unit (CPU) root port a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH;
receive a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin; and
cause a connected device to enter into a power management state.

22. The PCH of claim 21 , the PCH comprising logic to:
transmit an acknowledgement message to the CPU root port; and
deassert the 3.3 volt GPIO pin.

23. The PCH of claim 21 , the PCH comprising logic to:
receive an indication from the CPU root port of an awakening from a power management state;
transmit a clock request received state message to the CPU root port; and
suppress the 3.3 volt GPIO pin from being asserted to prevent an attached device from entering into a power management state; and
transmit to the CPU root port a clock request message comprising a bit set to deassert the power management state.

24. The PCH of claim 21 , the PCH comprising logic to:
receive an

Assignees

• Intel Corp

Inventors

• Teoh Poh Thiam
• Hunsaker Mikal C
• Lim Su Wei
• Lee Gim Chong
• Loo Hooi Kar
• Kerisnan Shashitheren
• Tan Siang Lin
• Lee Ming Chew
• Wai Ngeok Kuan
• Lim Li Len

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title