System, apparatus and method for synchronizing multiple virtual link states over a package interconnect

Patent metadata

Field	Value
Publication number	US-12001353-B2
Application number	US-202217819390-A
Country	US
Kind code	B2
Filing date	Aug 12, 2022
Priority date	May 30, 2019
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a first protocol stack circuit comprising a first transaction layer and a first link layer;
a second protocol stack circuit comprising a second transaction layer and a second link layer;
an arbiter/multiplexer (ARB/MUX) coupled to the first protocol stack circuit and the second protocol stack circuit, the ARB/MUX to multiplex first information of the first protocol stack circuit and second information of the second protocol stack circuit, wherein the ARB/MUX comprises:
a first virtual link state machine (vLSM) for the first link layer, the first vLSM associated with and to virtualize a link state of the first link layer; and
a second vLSM for the second link layer, the second vLSM associated with and to virtualize a link state of the second link layer;

wherein the first vLSM is to:
send a first status synchronization message, the first status synchronization message to identify a link state of the first vLSM; and
receive a second status synchronization message, the second status synchronization message to identify a link state of a third vLSM, wherein based at least in part on the link state of the first vLSM and the link state of the third vLSM, the ARB/MUX is to determine a resolved vLSM state.

2. The apparatus of claim 1 , wherein the ARB/MUX is to determine the resolved vLSM state to be a common link state to which the first vLSM and the third vLSM are resolved.

3. The apparatus of claim 2 , wherein the ARB/MUX is to determine the common link state to be an active state when the link state of the first vLSM is the active state and the link state of the third vLSM is a reset state.

4. The apparatus of claim 2 , wherein the ARB/MUX is to determine the common link state to be an active state when the link state of the first vLSM is the active state and the link state of the third vLSM is a retrain state.

5. The apparatus of claim 1 , wherein the first vLSM is to send the first status synchronization message comprising a physical layer packet.

6. The apparatus of claim 5 , wherein the first vLSM is to send the physical layer packet comprising a double word packet.

7. The apparatus of claim 1 , wherein:
the first vLSM is to send a state control request to the third vLSM to indicate that the first vLSM is to enter into a first vLSM state; and
in response to the state control request, the third vLSM is to send a status message to indicate that the third vLSM is in the first vLSM state.

8. The apparatus of claim 1 , further comprising a sideband interface to communicate sideband information with a device to couple to the apparatus via a link, the apparatus comprising the third vLSM.

9. The apparatus of claim 8 , wherein the sideband interface is to communicate the sideband information on a second link separate from the link.

10. The apparatus of claim 1 , wherein the first vLSM is to perform a synchronization protocol with the third vLSM while the first transaction layer is in a low power state.

11. A method comprising:
multiplexing, in an arbiter/multiplexer (ARB/MUX) of a first device, first information of a first protocol stack circuit and second information of a second protocol stack circuit, the ARB/MUX comprising:
a first virtual link state machine (vLSM) for a first link layer, the first vLSM associated with and to virtualize a link state of the first link layer; and
a second vLSM for a second link layer, the second vLSM associated with and to virtualize a link state of the second link layer, the first device comprising the first protocol stack circuit comprising a first transaction layer and the first link layer and the second protocol stack circuit comprising a second transaction layer and the second link layer;

sending, from the first vLSM, a first status synchronization message, the first status synchronization message to identify a link state of the first vLSM;
receiving a second status synchronization message, the second status synchronization message to identify a link state of a third vLSM; and
based at least in part on the link state of the first vLSM and the link state of the third vLSM, determining a resolved vLSM state.

12. The method of claim 11 , further comprising determining the resolved vLSM state to be a common link state.

13. The method of claim 12 , further comprising determining the common link state to be an active state when the link state of the first vLSM is the active state and the link state of the third vLSM is a reset state.

14. The method of claim 12 , further comprising determining the common link state to be an active state when the link state of the first vLSM is the active state and the link state of the third vLSM is a retrain state.

15. The method of claim 12 , further comprising sending, from the first vLSM, the first status synchronization message comprising a double word physical layer packet.

16. The method of claim 12 , further comprising sending, from the first device, sideband information to a second device, the second device comprising the third vLSM.

17. A system comprising:
a first processor having a first plurality of processor cores;
a second processor having a second plurality of processor cores; and
a point-to-point interconnect to couple the first processor with the second processor, wherein the first processor further comprises:
a first protocol stack circuit comprising a first transaction layer and a first link layer;
a second protocol stack circuit comprising a second transaction layer and a second link layer;
an arbiter/multiplexer (ARB/MUX) coupled to the first protocol stack circuit and the second protocol stack circuit, the ARB/MUX to multiplex first information of the first protocol stack circuit and second information of the second protocol stack circuit, wherein the ARB/MUX comprises:
a first virtual link state machine (vLSM) for the first link layer, the first vLSM associated with and to virtualize a link state of the first link layer; and
a second vLSM for the second link layer, the second vLSM associated with and to virtualize a link state of the second link layer;

wherein the first vLSM is to:
send a first status synchronization message to a third vLSM, the first status synchronization message to identify a link state of the first vLSM; and
receive a second status synchronization message, the second status synchronization message to identify a link state of the third vLSM, wherein based at least in part on the link state of the first vLSM and the link state of the third vLSM, the ARB/MUX is to determine a resolved vLSM state.

18. The system of claim 17 , wherein the ARB/MUX is to determine the resolved vLSM state to be a common link state to which the first vLSM and the third vLSM are resolved.

19. The system of claim 18 , wherein the ARB/MUX is to determine the common link state to be an active state when the link state of the first vLSM is the active state and the link state of the third vLSM is a reset state.

20. The system of claim 17 , wherein the first vLSM is to send the first status synchronization message comprising a double word physical layer packet.

Assignees

• Intel Corp

Inventors

• Hor Joon Teik
• Song Ting Lok
• Wagh Mahesh
• Lim Su Wei

Classifications

• G06F13/1652 Primary

  in a multiprocessor architecture (interprocessor communication using common memory G06F15/167) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4269

  using a handshaking protocol, e.g. Centronics connection · CPC title