Virtualized link states of multiple protocol layer package interconnects

Patent metadata

Field	Value
Publication number	US-11663154-B2
Application number	US-202217721413-A
Country	US
Kind code	B2
Filing date	Apr 15, 2022
Priority date	Apr 2, 2019
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

First claim

What is claimed is:

1. An apparatus comprising:
arbitration and multiplexer (ARB/MUX) circuitry to:
arbitrate data from a plurality of different link layers of a plurality of different protocols of an interconnect;
multiplex data of the plurality of different link layers on a physical layer of the interconnect;
maintain a first virtual link state machine (VLSM) for a first one of the plurality of link layers;
maintain a second VLSM for a second one of the plurality of link layers;

wherein states in the first VLSM and the second VLSM correspond to states defined in a link state machine of the physical layer.

2. The apparatus of claim 1 , wherein the ARB/MUX circuitry is to transition from one state in the first VLSM to another state in the first VLSM.

3. The apparatus of claim 2 , wherein the ARB/MUX circuitry is to identify a request by the first link layer for a link state transition, and the transition from the one state to the other state in the first VLSM is based on the request.

4. The apparatus of claim 3 , wherein the request comprises a state transition request sent from a first die to a second die over the interconnect, and the first die comprises the ARB/MUX circuitry.

5. The apparatus of claim 4 , wherein the second die comprises other ARB/MUX circuitry and the state transition request is sent from the ARB/MUX circuitry of the first die to the other ARB/MUX circuitry of the second die.

6. The apparatus of claim 2 , wherein the ARB/MUX circuitry is to send a state change request to the physical layer based on the transition from the one state to the other state.

7. The apparatus of claim 6 , wherein the state change request is to identify a particular state in the link state machine of the physical layer.

8. The apparatus of claim 7 , wherein the ARB/MUX circuitry is to:
identify a current state of the first VLSM;
identify a current state of the second VLSM, wherein the particular state is identified based on the current state of the first VLSM and the current state of the second VLSM.

9. The apparatus of claim 1 , wherein the first VLSM and the second VLSM each define a respective plurality of states.

10. The apparatus of claim 9 , wherein the plurality of states comprises a reset state, an active state, a power savings state, a sleep state, a link reset state, and a link error state.

11. The apparatus of claim 1 , wherein the interconnect comprises a multi-lane, point-to-point interconnect.

12. The apparatus of claim 1 , wherein one of the plurality of link layers comprises a PCIe-based link layer.

13. The apparatus of claim 12 , wherein another one of the plurality of link layers comprises a link layer of a cache coherent protocol.

14. A method comprising:
arbitrating, at a first die, data from a plurality of different link layers of a plurality of different protocols supported by the first die;
multiplexing data of the plurality of different link layers on a physical layer of an interconnect, wherein the interconnect couples the first die to a second die;
using a first virtual link state machine (VLSM) for a first one of the plurality of link layers;
using a second VLSM for a second one of the plurality of link layers, wherein states in the first VLSM and the second VLSM correspond to states defined in a link state machine of the physical layer.

15. A system comprising:
a first die;
a second die coupled to the first die by an interconnect, wherein the second die comprises arbitration and multiplexer (ARB/MUX) circuitry to:
arbitrate data from a plurality of different link layers of a plurality of different protocols of the interconnect;
multiplex data of the plurality of different link layers on a common physical layer of the interconnect;
maintain a first virtual link state machine (VLSM) for a first one of the plurality of link layers;
maintain a second VLSM for a second one of the plurality of link layers;

wherein states in the first VLSM and the second VLSM correspond to states defined in a link state machine of the physical layer.

16. The system of claim 15 , wherein the first die comprises a host processor and the second die comprises an accelerator.

17. The system of claim 15 , wherein the common physical layer is based on a PCIe physical layer.

Assignees

• Intel Corp

Inventors

• Hor Joon Teik
• Song Ting Lok
• Wagh Mahesh
• Lim Su Wei

Classifications

• G06F13/4031 Primary

  with arbitration · CPC title

• G06F13/387 Primary

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F13/1652

  in a multiprocessor architecture (interprocessor communication using common memory G06F15/167) · CPC title

• G06F13/4265

  on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title