Intrinsic temperature measurement for cross temperature handling in memory devices
US-2026093302-A1 · Apr 2, 2026 · US
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Lang Murong patents
Lang Murong is listed as an inventor on 220 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lang Murong |
| Total patents | 220 |
| First publication | Sep 7, 2017 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Select gate maintenance with adaptive scan frequency in a memory sub-system
US-2026088114-A1 · Mar 26, 2026 · US
Model based error avoidance
US-2026079828-A1 · Mar 19, 2026 · US
Adaptive scans of memory devices of a memory sub-system
US-12572298-B2 · Mar 10, 2026 · US
Machine-learning-based system health monitoring of a memory device
US-12572418-B2 · Mar 10, 2026 · US
Optimizing data reliability using erase retention
US-2026064281-A1 · Mar 5, 2026 · US
Selective media scanning for a virtual block
US-2026066020-A1 · Mar 5, 2026 · US
Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system
US-12554435-B2 · Feb 17, 2026 · US
Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system
US-12554403-B2 · Feb 17, 2026 · US
Adaptive read disturb scan for asymmetric blocks
US-2026038608-A1 · Feb 5, 2026 · US
Recent patents
Latest publications not already listed above.
Memory sub-system for adjusting memory device programming parameters
US-2026037126-A1 · Feb 5, 2026 · US
High reliability media management operations
US-2026037137-A1 · Feb 5, 2026 · US
Failure mode-adaptive low-density parity check soft decoding
US-2026039314-A1 · Feb 5, 2026 · US
Machine-learning-based system health monitoring of a memory device
US-2026037372-A1 · Feb 5, 2026 · US
Temperature-based read disturb operations
US-2026038607-A1 · Feb 5, 2026 · US
Determining voltage offset for a memory operation using memory bin and memory position
US-2026037145-A1 · Feb 5, 2026 · US
Efficient empty page scan operations
US-2026031161-A1 · Jan 29, 2026 · US
Migrating data based on wordline information in a memory sub-system
US-2026029926-A1 · Jan 29, 2026 · US
Wordline group dependent corrective program verify operation in a memory device
US-2026031151-A1 · Jan 29, 2026 · US
Corrective program convergence associated with memory cells of a memory sub-system
US-2026031164-A1 · Jan 29, 2026 · US
Partial block read level design for a memory system
US-2026031154-A1 · Jan 29, 2026 · US
All levels program operation integrated with corrective program verify operation in a memory device
US-2026031163-A1 · Jan 29, 2026 · US
Floating gate-based partial block handling in a memory sub-system
US-2026024591-A1 · Jan 22, 2026 · US
Dynamic read disturb handling using selective scanning
US-2026024594-A1 · Jan 22, 2026 · US
Cross temperature read voltage calibration for a memory system
US-2026024590-A1 · Jan 22, 2026 · US
Dynamic read calibration
US-2026011393-A1 · Jan 8, 2026 · US
Model based error avoidance
US-12517816-B2 · Jan 6, 2026 · US
Adaptive scanning of memory devices with supervised learning
US-12517659-B2 · Jan 6, 2026 · US
Block family management for a virtual block
US-12511080-B1 · Dec 30, 2025 · US
Select gate maintenance with adaptive scan frequency in a memory sub-system
US-12505894-B2 · Dec 23, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 213 |
| Sandisk Technologies Llc | 5 |
| Sandisk Technologies Inc | 2 |
| Micron Technology Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/26 | 111 |
| G11C16/0483 | 92 |
| G06F3/0679 | 79 |
| G11C29/028 | 74 |
| G11C16/08 | 72 |