Select gate maintenance with adaptive scan frequency in a memory sub-system

Patent metadata

Field	Value
Publication number	US-12505894-B2
Application number	US-202318384716-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Nov 9, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device. The processing device updates, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.

First claim

What is claimed is:

1 . A system comprising:
a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising:
determining a number of program/erase cycles performed on a block of the memory device;
determining that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block;
performing a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block;
responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, determining a rate of change associated with the current threshold voltage of the at least one select gate device; and
updating, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.

2 . The system of claim 1 , wherein determining that the number of program/erase cycles performed on the block satisfies the first threshold condition comprises:
determining that the number of program/erase cycles performed on the block is greater than or equal to a threshold number of program/erase cycles, wherein the threshold number of program/erase cycles is equal to the frequency interval for performing a threshold voltage integrity scan on the block.

3 . The system of claim 1 , wherein performing the threshold voltage integrity scan on the block comprises:
applying one or more read voltages to the at least one select gate device of the block; receiving one or more output values based on the one or more read voltages; and comparing the one or more output values to an expected output value based on a target threshold voltage.

4 . The system of claim 1 , wherein the processing device to perform further operations comprising:
comparing the error count associated with the current threshold voltage of the at least one select gate device to the second threshold criterion, wherein the error count satisfies the second threshold criterion when the error count is less than a threshold error count.

5 . The system of claim 1 , wherein updating the frequency interval comprises:
retrieving a look-up table, wherein the look-up table comprises one or more entries, each entry associated with a respective predefined frequency interval and an associated respective rate of change threshold window; comparing a value of the rate of change to each of the respective rate of change threshold windows of the one or more entries; determining that the value of the rate of change is within a first rate of change threshold window of a first entry; identifying a first predefined frequency interval associated with the first rate of change threshold window of the first entry; and updating the frequency interval with the first predefined frequency interval.

6 . The system of claim 1 , wherein the processing device to perform further operations comprising:
responsive to determining that the error count associated with the current threshold voltage of the at least one select gate device does not satisfy the second threshold criterion, performing a touch up operation on the at least one select gate device to adjust the current threshold voltage to a target threshold voltage.

7 . The system of claim 1 , wherein the processing device to perform further operations comprising:
responsive to determining that the error count associated with the current threshold voltage of the at least one select gate device does not satisfy the second threshold criterion, retiring the block.

8 . A method comprising:
identifying a frequency interval for performing a threshold voltage integrity scan on a block of a memory device; determining that a first number of program/erase cycles performed on the block satisfies the frequency interval; performing a first threshold voltage integrity scan on the block to determine a first error count associated with a current threshold voltage of at least one select gate device of the block; responsive to the first error count associated with the current threshold voltage of the at least one select gate device satisfying a threshold criterion, determining a rate of change associated with the current threshold voltage of the at least one select gate device; updating, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block; determining that a second number of program/erase cycles performed on the block satisfies the updated frequency interval; and performing a second threshold voltage integrity scan on the block to determine a second error count associated with a current threshold voltage of the at least one select gate device of the block.

9 . The method of claim 8 , wherein determining that the first number of program/erase cycles performed on the block satisfies the frequency interval comprises:
determining that the first number of program/erase cycles performed on the block is greater than or equal to a threshold number of program/erase cycles, wherein the threshold number of program/erase cycles is equal to the frequency interval for performing a threshold voltage integrity scan on the block.

10 . The method of claim 8 , wherein performing the first threshold voltage integrity scan on the block comprises:
applying one or more read voltages to the at least one select gate device of the block; receiving one or more output values based on the one or more read voltages; and comparing the one or more output values to an expected output value based on a target threshold voltage.

11 . The method of claim 8 , further comprising:
comparing the first error count associated with the current threshold voltage of the at least one select gate device to the threshold criterion, wherein the first error count satisfies the threshold criterion when the first error count is less than a threshold error count.

12 . The method of claim 8 , wherein updating the frequency interval comprises:
retrieving a look-up table, wherein the look-up table comprises one or more entries, each entry associated with a respective predefined frequency interval and an associated respective rate of change threshold window; comparing a value of the rate of change to each of the respective rate of change threshold windows of the one or more entries; determining that the value of the rate of change is within a first rate of change threshold window of a first entry; identifying a first predefined frequency interval associated with the first rate of change threshold window of the first entry; and updating the frequency interval with the first predefined frequency interval.

13 . The method of claim 8 , further comprising:
responsive to determining that the first error count associated with the current threshold voltage of the at least one select gate device does not satisfy the threshold criterion, performing a touch up operation on the at least one select gate device to adjust the current threshold voltage to a target threshold voltage.

14 . The method of claim 8 , further comprising:
responsive to determining that the first error count associated with the current threshold voltage of the at least one select gate device does not satisfy the threshold criterion, retiring the block.

15 . A non-transitory computer-readable storage medium comprising instructions that, when e

Assignees

• Micron Technology Inc

Inventors

• Xu Zhongguang
• Lang Murong

Classifications

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title