Power distribution networks for a three-dimensional (3d) integrated circuit (ic) (3dic)

Patent metadata

Field	Value
Publication number	US-2019027435-A1
Application number	US-201816144127-A
Country	US
Kind code	A1
Filing date	Sep 27, 2018
Priority date	Mar 29, 2017
Publication date	Jan 24, 2019
Grant date	—

Abstract

Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

First claim

What is claimed is:

1 . A three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:
a first IC tier; a second IC tier; and a power distribution path extending from the first IC tier to the second IC tier, wherein the power distribution path comprises a first top metal layer in the first IC tier and a second top metal layer in the second IC tier, wherein the first top metal layer is at least three micrometers (3 μm) thick.

2 . The 3DIC of claim 1 , wherein the second top metal layer is at least 3 μm thick.

3 . The 3DIC of claim 1 , further comprising a via electrically coupling the first top metal layer to the second top metal layer.

4 . The 3DIC of claim 3 , wherein the via comprises a through silicon via (TSV).

5 . The 3DIC of claim 3 , wherein the via comprises a through oxide via (TOV).

6 . The 3DIC of claim 1 , wherein a plurality of vias electrically couple the first top metal layer to the second top metal layer.

7 . The 3DIC of claim 6 , wherein the plurality of vias form two via walls around a logical circuit in the first IC tier.

8 . The 3DIC of claim 6 , wherein at least one of the plurality of vias is positioned inside a logical circuit in the first IC tier.

9 . The 3DIC of claim 6 , wherein a first subset of the plurality of vias is configured to be coupled to a first reference voltage source and a second subset of the plurality of vias is configured to be coupled to a second reference voltage source.

10 . The 3DIC of claim 9 , wherein the plurality of vias are arranged in a plurality of rows where alternating rows are coupled to the first reference voltage source and the second reference voltage source, respectively.

11 . The 3DIC of claim 10 , wherein the alternating rows are staggered relative to one another.

12 . A three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:
a first means for containing a first circuit on a first IC tier; a second means for containing a second circuit on a second IC tier; and a means for distributing power extending from the first IC tier to the second IC tier, wherein the means for distributing power comprises a first top metal layer in the first IC tier and a second top metal layer in the second IC tier, wherein the first top metal layer is at least three micrometers (3 μm) thick.

Assignees

• Qualcomm Inc

Inventors

• Kamal Pratyush
• Samadi Kambiz
• Xie Jing
• Du Yang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title