Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits

Patent metadata

Field	Value
Publication number	US-9508615-B2
Application number	US-201514617901-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Feb 9, 2015
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

First claim

What is claimed is:

1. A method for pre-bond testing a three-dimensional integrated circuit, comprising:
building a fully connected two-dimensional (2D) clock tree on a backbone die;
building multiple isolated 2D clock trees on one or more non-backbone die, wherein multiple through-silicon-vias connect the 2D clock tree in the backbone die and the multiple isolated 2D clock trees in the one or more non-backbone die; and
connecting the multiple isolated 2D clock trees in the one or more non-backbone die using a Detachable tree (D-tree), wherein the D-tree comprises a root node and fuses located at sinks associated with the isolated 2D clock trees.

2. The method recited in claim 1 , further comprising:
pre-bond testing the one or more non-backbone die using a single clock probe pad, wherein the single clock probe pad used to pre-bond test the one or more non-backbone die corresponds to the root node associated with the D-tree that connects the multiple isolated 2D clock trees on the one or more non-backbone die.

3. The method recited in claim 2 , wherein the backbone die and the one or more non-backbone die are separated and tested individually during the pre-bond testing.

4. The method recited in claim 2 , further comprising:
removing the D-tree from the one or more non-backbone die subsequent to the pre-bond testing, wherein removing the D-tree from the one or more non-backbone die comprises burning the fuses at the sinks associated with the 2D clock trees.

5. The method recited in claim 1 , wherein the one or more non-backbone die comprise N sinks, where N equals a number of the multiple isolated 2D clock trees on the one or more non-backbone die.

6. The method recited in claim 1 , wherein the one or more non-backbone die comprise N sinks, where N is greater than one and less than a number of the multiple isolated 2D clock trees on the one or more non-backbone die.

7. The method recited in claim 1 , further comprising:
determining that a number of the isolated 2D clock trees in at least one of the one or more non-backbone die exceeds a threshold value; and
reducing a number of the fuses located at the sinks associated with the isolated 2D clock trees in the at least one non-backbone die such that the reduced number of fuses in the at least one non-backbone die is less than the number of the isolated 2D clock trees in the at least one non-backbone die.

8. The method recited in claim 1 , wherein the D-tree comprises a rectilinear minimum spanning tree that represents a shortest interconnect among the sinks associated with the multiple isolated 2D clock trees in the one or more non-backbone die.

9. The method recited in claim 1 , wherein the D-tree comprises a non-buffered Steiner tree built using a Steiner router configured to minimize wirelength and buffer overhead associated with the D-tree.

10. A three-dimensional (3D) stacked integrated circuit, comprising:
a backbone die, wherein the backbone die comprises a clock source and a fully connected two-dimensional (2D) clock tree;
one or more non-backbone die that each have multiple isolated 2D clock trees, wherein the multiple isolated 2D clock trees in the one or more non-backbone die are connected to one another with a Detachable tree (D-tree) that comprises a single clock probe pad and fuses attached at sinks associated with the isolated 2D clock trees; and
multiple through-silicon-vias that connect the fully connected 2D clock tree in the backbone die to the multiple isolated 2D clock trees in the one or more non-backbone die.

11. The 3D stacked integrated circuit recited in claim 10 , wherein the single clock probe pad associated with the D-tree is used to pre-bond test the one or more non-backbone die.

12. The 3D stacked integrated circuit recited in claim 11 , wherein the backbone die and the one or more non-backbone die are separated and tested individually during the pre-bond test.

13. The 3D stacked integrated circuit recited in claim 11 , wherein the fuses associated with the D-tree are burned subsequent to the pre-bond test to remove the D-tree from the one or more non-backbone die.

14. The 3D stacked integrated circuit recited in claim 10 , wherein the one or more non-backbone die comprise N sinks, where N equals a number of the multiple isolated 2D clock trees on the one or more non-backbone die.

15. The 3D stacked integrated circuit recited in claim 10 , wherein the one or more non-backbone die comprise N sinks, where N is greater than one and less than a number of the multiple isolated 2D clock trees on the one or more non-backbone die.

16. The 3D stacked integrated circuit recited in claim 10 , wherein the D-tree comprises a rectilinear minimum spanning tree that represents a shortest interconnect among the sinks associated with the multiple isolated 2D clock trees in the one or more non-backbone die.

17. The 3D stacked integrated circuit recited in claim 10 , wherein the D-tree is built using a Steiner router configured to minimize wirelength and buffer overhead associated with the D-tree.

18. A three-dimensional (3D) stacked integrated circuit, comprising:
a first die comprising a fully connected two-dimensional (2D) clock tree; and
a second die bonded to the first die, wherein the second die comprises multiple isolated 2D clock trees that are connected to the fully connected 2D clock tree in the first die using multiple through-silicon-vias, and wherein the second die further comprises a non-buffered clock tree that has one or more burned fuses.

19. The 3D stacked integrated circuit recited in claim 18 , wherein the burned fuses are located at sinks associated with the multiple isolated 2D clock trees in the second die.

20. The 3D stacked integrated circuit recited in claim 18 , wherein the burned fuses are located at internal nodes associated with the non-buffered clock tree.

Assignees

• Qualcomm Inc

Inventors

• Lim Sung Kyu
• Samadi Kambiz
• Kamal Pratyush
• Du Yang

Classifications

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title