Apparatuses and methods for speculative execution side channel mitigation
US-2020133679-A1 · Apr 30, 2020 · US
US11620229B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11620229-B2 |
| Application number | US-202016797476-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 21, 2020 |
| Priority date | Feb 21, 2020 |
| Publication date | Apr 4, 2023 |
| Grant date | Apr 4, 2023 |
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Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.
Opening claim text (preview).
What is claimed is: 1. A data cache comprising: a plurality of cache lines, at least one cache line comprising: a data field; a tag field; a way predictor field; and a prediction hint field, wherein the prediction hint field stores an alternate instruction behavior and an instruction of a pre-determined instruction type, wherein the alternate instruction behavior is performed responsive to a determination that an issued instruction matches the instruction. 2. The data cache of claim 1 , wherein the prediction hint field is integrated with the tag field. 3. The data cache of claim 1 , wherein the prediction hint field is integrated with the way predictor field. 4. The data cache of claim 1 , wherein the data cache is a LI data cache. 5. The data cache of claim 1 , wherein the pre-determined instruction type is an instruction which is repeatedly being re-executed. 6. The data cache of claim 1 , wherein the at least one cache line is a subset of the plurality of cache lines. 7. The data cache of claim 1 , wherein the alternate instruction behavior is a disable load data return in response to unknown Read-After-Write hazard. 8. The data cache of claim 1 , wherein the alternate instruction behavior is a speculative store bypass disable. 9. The data cache of claim 1 , wherein certain prediction hint fields are unpopulated. 10. A data cache comprising: a data array; a tag array; a way predictor field; and a prediction hint field, wherein the prediction hint field stores alternate instruction behavior and an instruction of a pre-determined instruction type, wherein the alternate instruction behavior is performed responsive to a determination that an issued instruction matches the instruction. 11. The data cache of claim 10 , wherein each entry of the tag array has an integrated prediction hint field. 12. The data cache of claim 11 , wherein certain prediction hint fields are unpopulated. 13. The data cache of claim 10 , wherein each entry in the way predictor array has an integrated prediction hint field. 14. The data cache of claim 10 , wherein the alternate instruction behavior is a disable load data return in response to unknown Read-After-Write hazard. 15. The data cache of claim 10 , wherein the alternate instruction behavior is a speculative store bypass disable. 16. The data cache of claim 10 , wherein the alternate instruction behavior is an alternate instruction. 17. A method for providing prediction hints using a data cache, the method comprising: storing alternate instruction behavior and an instruction of a pre-determined instruction type in a prediction hint element for certain cache lines in a way predictor of the data cache; comparing an issued instruction to the instruction stored in the prediction hint element; and performing the alternate instruction behavior responsive to a determination that an issued instruction matches the instruction. 18. The method of claim 17 , wherein the alternate instruction behavior is a disable load data return in response to unknown Read-After-Write hazard. 19. The method of claim 18 , wherein the alternate instruction behavior is a speculative store bypass disable. 20. The method of claim 19 , wherein the pre-determined instruction type is an instruction which is repeatedly being re-executed.
of operating mode, e.g. cache mode or local memory mode · CPC title
Prefetching based on hints or prefetch instructions · CPC title
using selective caching, e.g. bypass · CPC title
with prefetch · CPC title
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