Logging guest physical address for memory access faults

Patent metadata

Field	Value
Publication number	US-12367154-B2
Application number	US-202218086635-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Dec 22, 2021
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Systems and methods are disclosed for logging guest physical address for memory access faults. For example, a method for logging guest physical address includes receiving a first address translation request from a processor pipeline at a translation lookaside buffer for a first guest virtual address; identifying a hit with a fault condition corresponding to the first guest virtual address; responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address.

First claim

What is claimed is:

1. An integrated circuit comprising:
a processor pipeline configured to fetch and execute instructions, including load instructions and store instructions;
a translation lookaside buffer configured to perform two-stage address translation to translate guest virtual addresses to physical addresses, wherein an entry of the translation lookaside buffer includes a tag that includes a guest virtual address and data that includes a physical address;
a data store configured to:
hold a guest physical address and the guest virtual address; and
store a guest fault flag indicating whether a fault condition corresponding to a first guest physical address occurred during a first stage or a second stage of the two-stage address translation; and

a fault handling circuitry that is configured to:
responsive to the fault condition on a hit in the translation lookaside buffer for a first address translation request from the processor pipeline for a first guest virtual address, invoke a single-stage page table walk with the first guest virtual address to obtain the first guest physical address; and
store the first guest physical address with the first guest virtual address in the data store.

2. The integrated circuit of claim 1 , in which the fault handling circuitry is configured to:
transfer the first guest physical address from the data store to a control status register in response to the fault condition being on an entry of the translation lookaside buffer with the tag that includes the guest virtual address matching the first guest virtual address stored in the data store.

3. The integrated circuit of claim 2 , comprising:
an exception handling circuitry configured to update a processor core that includes the processor pipeline in response to exceptions occurring in the processor core, in which the first guest physical address is transferred to the control status register via a signal path through the translation lookaside buffer and the exception handling circuitry.

4. The integrated circuit of claim 2 , comprising:
a memory storing hypervisor software that is configured to read the control status register in response to receiving an exception from a processor core including the processor pipeline.

5. The integrated circuit of claim 1 , in which the fault handling circuitry is configured to:
cause the translation lookaside buffer to return a miss to the processor pipeline in response the first address translation request.

6. The integrated circuit of claim 5 , in which the processor pipeline is configured to:
in response to the miss, add the first address translation request to a queue of address translation requests to be retried in program order.

7. The integrated circuit of claim 1 , in which the data store is configured to store a valid flag, and in which the fault handling circuitry is configured to:
update the valid flag to indicate the first guest physical address is ready when storing the first guest physical address in the data store; and
update the valid flag to indicate the first guest physical address is not ready responsive to transferring the first guest physical address to a control status register.

8. A method comprising:
receiving, by a translation lookaside buffer, a first address translation request from a processor pipeline at the translation lookaside buffer for a first guest virtual address;
identifying, by the translation lookaside buffer, a hit and a fault condition corresponding to the first guest virtual address;
responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address;
storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address; and
storing, in the data store, a guest fault flag indicating whether the fault condition corresponding to the first guest physical address occurred during a first stage or a second stage of a two-stage address translation.

9. The method of claim 8 , comprising:
transferring the first guest physical address from the data store to a control status register in response to the fault condition being on an entry of the translation lookaside buffer with the tag that includes the guest virtual address matching the first guest virtual address stored in the data store.

10. The method of claim 9 , in which the control status register is read by hypervisor software in response to receiving an exception from a processor core including the processor pipeline.

11. The method of claim 8 , comprising:
returning a miss to the processor pipeline in response the first address translation request.

12. The method of claim 11 , comprising:
in response to the miss, adding the first address translation request to a queue of address translation requests to be retried in program order.

13. The method of claim 8 , in which the data store is configured to store a valid flag, comprising:
updating the valid flag to indicate the first guest physical address is ready when storing the first guest physical address in the data store; and
updating the valid flag to indicate the first guest physical address is not ready responsive to transferring the first guest physical address to a control status register.

14. An integrated circuit comprising:
a processor pipeline configured to fetch and execute instructions, including load instructions and store instructions;
a translation lookaside buffer configured to perform two-stage address translation to translate guest virtual addresses to physical addresses, wherein an entry of the translation lookaside buffer includes a tag that includes a guest virtual address and data that includes a physical address;
a data store configured to:
hold a guest physical address and the guest virtual address; and
store a guest fault flag indicating whether a fault condition corresponding to a first guest physical address occurred during a first stage or a second stage of the two-stage address translation; and

a fault handling circuitry that is configured to:
responsive to the fault condition on a hit in the translation lookaside buffer for a first address translation request from the processor pipeline for a first guest virtual address, invoke a single-stage page table walk with the first guest virtual address to obtain the first guest physical address;
cause the translation lookaside buffer to return a miss to the processor pipeline in response the first address translation request; and
store the first guest physical address with the first guest virtual address in the data store.

15. The integrated circuit of claim 14 , in which the fault handling circuitry is configured to:
transfer the first guest physical address from the data store to a control status register in response to the fault condition being on an entry of the translation lookaside buffer with the tag that includes the guest virtual address matching the first guest virtual address stored in the data store.

16. The integrated circuit of claim 15 , comprising:
an exception handling circuitry configured to update a processor core that includes the processor pipeline in response to exceptions occurring in the processor core, in which the first guest physical address is transferred to the control status register via a signal path through the translation lookaside buffer and the exception handling circuitry.

Assignees

• Sifive Inc

Inventors

• Ingalls John
• Waterman Andrew

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/1024

  Latency reduction · CPC title