Parameter collapsing and corner reduction in an integrated circuit

Patent metadata

Field	Value
Publication number	US-10296704-B2
Application number	US-201815959398-A
Country	US
Kind code	B2
Filing date	Apr 23, 2018
Priority date	Jun 13, 2017
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

First claim

What is claimed is:

1. A computer program product using a computing device to reduce a runtime overhead needed for testing of an integrated circuit design, the computer program product comprising:
one or more non-transitory computer-readable storage media and program instructions stored on the one or more non-transitory computer-readable storage media, the program instructions, when executed by the computing device, cause the computing device to perform a method comprising:
determining, by the computing device, parameters that clock routing and data routing in an integrated circuit are dependent upon, the parameters comprising any source of variation in the integrated circuit which impact a delay or slew of voltage through the integrated circuit;
determining, by the computing device, whether the parameters are suitable for compaction by determining whether the parameters are utilized in only one of clock routing and data routing;
redefining, by the computing device, the parameters suitable for compaction into at least one proxy compacted parameter containing a lesser number of parameters to lower a number of parameters tested;
performing, by the computing device, a path-based or a block-based statistical static timing analysis for the integrated circuit using the at least one proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction;
generating an updated circuit design for the integrated circuit if the integrated circuit design fails the statistical static timing analysis; and
fabricating the updated circuit design,
wherein the parameters are selected from a group consisting of one or more of the following: variation in a thickness of a fabricated component in the integrated circuit, variation in a wire segment or silicon transistor shape in the integrated circuit, variation in dopants or implants utilized in the manufacture of the integrated circuit, variations in device threshold voltage, variations in supply voltage for the integrated circuit, variations in device threshold voltage, variations in supply voltage for the integrated circuit, and variations in a temperature across the integrated circuit.

Assignees

• IBM

Inventors

• Foreman Eric
• Hemmett Jeffrey

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title