Differential pipeline delays in a coprocessor
US-12333309-B2 · Jun 17, 2025 · US
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Fleischman Jay patents
Fleischman Jay is listed as an inventor on 34 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fleischman Jay |
| Total patents | 34 |
| First publication | Feb 2, 2017 |
| Latest publication | Jun 17, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Register based SIMD lookup table operations
US-12299445-B2 · May 13, 2025 · US
Selective speculative prefetch requests for a last-level cache
US-12282428-B2 · Apr 22, 2025 · US
System probe aware last level cache insertion bypassing
US-12204454-B2 · Jan 21, 2025 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-12153926-B2 · Nov 26, 2024 · US
N-way fault tolerant processing system
US-2024320050-A1 · Sep 26, 2024 · US
Large number integer addition using vector accumulation
US-2024319964-A1 · Sep 26, 2024 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-2024126552-A1 · Apr 18, 2024 · US
Systems and methods for interpolating register-based lookup tables
US-2024095180-A1 · Mar 21, 2024 · US
Differential pipeline delays in a coprocessor
US-2024045694-A1 · Feb 8, 2024 · US
Recent patents
Latest publications not already listed above.
Processor-guided execution of offloaded instructions using fixed function operations
US-11868777-B2 · Jan 9, 2024 · US
Re-fetching data for L3 cache data evictions into a last-level cache
US-11847062-B2 · Dec 19, 2023 · US
Register based simd lookup table operations
US-2023393855-A1 · Dec 7, 2023 · US
Differential pipeline delays in a coprocessor
US-11709681-B2 · Jul 25, 2023 · US
Selective speculative prefetch requests for a last-level cache
US-2023205700-A1 · Jun 29, 2023 · US
Re-fetching data for l3 cache data evictions into a last-level cache
US-2023195643-A1 · Jun 22, 2023 · US
Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics
US-11567554-B2 · Jan 31, 2023 · US
System and method for page table caching memory
US-11550728-B2 · Jan 10, 2023 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-2022188117-A1 · Jun 16, 2022 · US
System probe aware last level cache insertion bypassing
US-2022050785-A1 · Feb 17, 2022 · US
System probe aware last level cache insertion bypassing
US-11163688-B2 · Nov 2, 2021 · US
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
US-11023241-B2 · Jun 1, 2021 · US
System and method for page table caching memory
US-2021097002-A1 · Apr 1, 2021 · US
System probe aware last level cache insertion bypassing
US-2021089462-A1 · Mar 25, 2021 · US
Scheduling memory bandwidth based on quality of service floorbackground
US-10700954-B2 · Jun 30, 2020 · US
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
US-2020065108-A1 · Feb 27, 2020 · US
Scheduling memory bandwidth based on quality of service floorbackground
US-2019190805-A1 · Jun 20, 2019 · US
Power conservation in a coprocessor
US-2019179396-A1 · Jun 13, 2019 · US
Differential pipline delays in a coprocessor
US-2019179643-A1 · Jun 13, 2019 · US
Mechanism for resource utilization metering in a computer system
US-10223162-B2 · Mar 5, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 34 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0811 | 10 |
| G06F9/3867 | 8 |
| Y02D10/00 | 8 |
| G06F12/084 | 8 |
| G06F9/3004 | 7 |