Scalable bandwidth non-volatile memory

Patent metadata

Field	Value
Publication number	US-11010061-B2
Application number	US-201916428802-A
Country	US
Kind code	B2
Filing date	May 31, 2019
Priority date	Sep 29, 2016
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

First claim

What is claimed is:

1. A device comprising:
a plurality of memory partitions, each of the plurality of memory partitions comprising:
a plurality of non-volatile memory arrays,
a data buffer to buffer data, and
access circuitry to access the plurality of non-volatile memory arrays; and

logic to:
determine a memory access spacing for each of a plurality of memory access commands according to one or more timing rules, the one or more timing rules to indicate command spacing based on access type of a memory access command and access type of a previous memory access command to a same partition of the plurality of memory partitions, and
queue the plurality of memory access commands with the determined memory access spacing for performance by the access circuitry of one or more of the plurality of memory partitions.

2. The device of claim 1 , wherein:
the one or more timing rules are to indicate a different command spacing for read commands and write commands.

3. The device of claim 1 , wherein:
the one or more timing rules are to indicate a different command spacing for sequential memory access commands to a same partition and sequential memory access commands to different partitions.

4. The device of claim 1 , wherein:
the plurality of memory partitions are independently operable.

5. The device of claim 1 , wherein:
each of the plurality of non-volatile memory arrays of each of the plurality of memory partitions includes a three-dimensional (3D) crosspoint array.

6. The device of claim 5 , wherein:
the 3D crosspoint array includes phase change memory (PCM) cells.

7. The device of claim 5 , wherein:
the 3D crosspoint array includes a chalcogenide material.

8. The device of claim 1 , wherein:
one or more of the plurality of memory partitions are to operate as a cache.

9. The device of claim 1 , wherein:
the device comprises a solid state drive (SSD).

10. The device of claim 1 , wherein:
the access circuitry of each of the plurality of memory partitions comprises one or more of a memory driver, a sense amplifier, and a sequencer.

11. An apparatus comprising:
interface circuitry coupled with a host and a plurality of memory partitions, each of the plurality of memory partitions comprising: a plurality of non-volatile memory arrays, a data buffer to buffer data, and access circuitry to access the plurality of non-volatile memory arrays, the interface circuitry to receive a plurality of memory access commands from the host; and
logic to:
determine a memory access spacing for each of a plurality of memory access commands according to one or more timing rules, the one or more timing rules to indicate command spacing based on access type of a memory access command and access type of a previous memory access command to a same partition of the plurality of memory partitions, and
queue the plurality of memory access commands with the determined memory access spacing for performance by the access circuitry of each of the plurality of memory partitions.

12. The apparatus of claim 11 , wherein:
the host comprises one or more of a processor and memory controller.

13. The apparatus of claim 11 , wherein:
the one or more timing rules are to indicate a different command spacing for read commands and write commands.

14. The apparatus of claim 11 , wherein:
the one or more timing rules are to indicate a different command spacing for sequential memory access commands to a same partition and sequential memory access commands to different partitions.

15. The apparatus of claim 11 , wherein:
the plurality of memory partitions are independently operable.

16. The apparatus of claim 11 , wherein:
each of the plurality of non-volatile memory arrays of each of the plurality of memory partitions includes a three-dimensional (3D) crosspoint array.

17. The apparatus of claim 16 , wherein:
the 3D crosspoint array includes phase change memory (PCM) cells.

18. A system comprising:
a processor;
a plurality of memory partitions, each of the plurality of memory partitions comprising:
a plurality of non-volatile memory arrays,
a data buffer to buffer data, and
access circuitry to access the plurality of non-volatile memory arrays; and

logic to:
determine a memory access spacing for each of a plurality of memory access commands according to one or more timing rules, the one or more timing rules to indicate command spacing based on access type of a memory access command and access type of a previous memory access command to a same partition of the plurality of memory partitions, and
queue the plurality of memory access commands with the determined memory access spacing for performance by the access circuitry of one or more of the plurality of memory partitions.

19. The system of claim 18 , wherein:
the plurality of memory partitions are on a same chip as the logic.

20. The system of claim 18 , wherein:
the processor is on the same chip as the plurality of memory partitions and the logic.

Assignees

• Intel Corp

Inventors

• Sundaram Rajesh
• Fazio Albert
• Kau Derchang
• Qawami Shekoufeh

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title